CY7C1614KV18-250BZI
Active and preferred

CY7C1614KV18-250BZI

Data Sheet
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CY7C1614KV18-250BZI
CY7C1614KV18-250BZI
Data Sheet

Product details

  • Architecture
    QDR-II
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1.5
Recommended
OPN
CY7C1614KV18-250BZI
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY7C1614KV18-250BZI is a 144-Mbit QDR II synchronous pipelined burst SRAM in a 4M × 36 organization with separate read and write ports. It supports two-word burst transfers with DDR interfaces and operates up to 250 MHz. Core supply is 1.8 V with VDDQ from 1.4 V to VDD. DOFF selects 1.5-cycle (QDR II) or 1-cycle (QDR I) read latency, and echo clocks plus an on-chip PLL aid timing.

Features

  • Dual read/write data ports
  • 360 MHz clock operation
  • DDR I/O, 720 MHz data transfer
  • Two-word burst on all accesses
  • Two input clocks K and K
  • Separate output clocks C and C
  • Echo clocks CQ and CQ
  • 1.5-cycle read latency (DOFF=1)
  • 1-cycle read latency (DOFF=0)
  • 1.8 V VDD supply
  • VDDQ = 1.4 V to VDD
  • IEEE 1149.1-2001 JTAG TAP

Benefits

  • No bus turnaround, more bandwidth
  • Concurrent reads and writes
  • Fast throughput at 360 MHz
  • Echo clocks ease data capture
  • C/C clocks reduce skew issues
  • Flexible latency eases timing
  • PLL improves data placement
  • JTAG simplifies board test
  • Port selects enable depth scaling
  • VDDQ range eases I/O matching
  • Defined power-up prevents faults
  • Low SER improves data integrity

Applications

Documents

Design resources

Partner solutions

Developer community

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