CY7C1520KV18-250BZCT
Active and preferred

CY7C1520KV18-250BZCT

Data Sheet
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CY7C1520KV18-250BZCT
CY7C1520KV18-250BZCT
Data Sheet

Product details

  • Density
    72 MBit
  • Family
    DDR-II CIO
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    2M x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
Recommended
OPN
CY7C1520KV18-250BZCT
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1520KV18-250BZCT is a 72-Mbit (2M × 36) synchronous pipelined DDR-II SRAM with two-word burst operation. It supports up to 250 MHz clocking (DDR transfers at 500 MHz) and selectable read latency: 1.5 cycles with PLL enabled (DOFF HIGH) or 1 cycle DDR-I mode with DOFF LOW. HSTL I/Os support 1.5 V/1.8 V VDDQ, with echo clocks (CQ/CQ), ZQ impedance match, and JTAG 1149.1 test access.

Features

  • 72-Mbit DDR-II sync SRAM
  • 333 MHz clock, 666 MHz data xfer
  • Two-word burst, 1-bit counter
  • 1.5-cycle read latency (DOFF HI)
  • 1-cycle read latency (DOFF LO)
  • Dual input clocks K/K
  • Dual output clocks C/C
  • Echo clocks CQ/CQ
  • Byte write via BWS signals
  • ZQ sets output impedance
  • PLL runs 120 MHz to fMAX
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • High bandwidth at 333 MHz clocks
  • Cuts addr bus rate with 2-word burst
  • Latency option fits DDR-I/DDR-II
  • Improves DDR timing with K/K clocks
  • Reduces skew using C/C clocks
  • Simplifies capture with CQ/CQ clocks
  • Byte writes avoid read-modify-write
  • Impedance control improves SI
  • PLL stabilizes high-speed timing
  • Depth expansion without wait states
  • Pipeline starts every K rising edge
  • Eases board test with JTAG scan

Applications

Documents

Design resources

Partner solutions

Developer community

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