CY7C1460KV25-250AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1460KV25-250AXC

Datasheet
package
ea.
in stock

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CY7C1460KV25-250AXC
CY7C1460KV25-250AXC
ea.
Datasheet

Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    36 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    2.38 V to 2.63 V
  • Organization (X x Y)
    1Mb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1460KV25-250AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C1460KV25-250AXC is a 36-Mbit (1M × 36) synchronous pipelined burst SRAM with NoBL architecture and on-chip ECC. It supports 250 MHz, zero-wait-state, back-to-back read/write transfers with registered inputs and outputs and 2.5 ns clock-to-output (tCO). The device uses 2.5 V core and I/O supplies, offers linear or interleaved 4-beat bursts, byte writes, and a ZZ sleep mode for data retention.

Features

  • 36-Mbit pipelined burst SRAM
  • NoBL architecture, zero wait states
  • 250 MHz bus operation supported
  • tCO max 2.5 ns (250 MHz grade)
  • Fully registered inputs and outputs
  • Linear or interleaved burst order
  • On-chip burst counter, 4-beat burst
  • Byte write enables (BWx) supported
  • Clock enable (CEN) stalls clock
  • ZZ sleep mode, IDDZZ max 75 mA
  • On-chip ECC corrects single-bit
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • High throughput per clock cycle
  • No wait states cuts access latency
  • 250 MHz supports fast datapaths
  • 2.5 ns tCO eases timing closure
  • Registered I/O simplifies interface
  • Burst modes match CPU/FPGA needs
  • 4-beat burst reduces addr toggling
  • Byte writes simplify RMW updates
  • CEN enables easy bus throttling
  • Sleep mode reduces standby power
  • ECC improves data reliability
  • JTAG speeds board test/debug
Documents

Design resources

Partner solutions

Developer community

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