CY62167G-45ZXIT
Active and preferred
RoHS Compliant
Lead-free

CY62167G-45ZXIT

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CY62167G-45ZXIT
CY62167G-45ZXIT

Product details

  • Density
    16 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    4.5 V to 5.5 V
  • Organization (X x Y)
    1M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
OPN
CY62167G-45ZXIT
Product Status active and preferred
Infineon Package
Package Name TSOP-I-48 (51-85183)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
Package Name TSOP-I-48 (51-85183)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62167G-45ZXIT is a 16-Mbit (1M × 16 or 2M × 8) CMOS static RAM with embedded ECC for single-bit error correction and Byte Power-down. It supports 45 ns access at 4.5 V to 5.5 V over the industrial range (−40°C to 85°C), with automatic power-down standby current up to 16 µA. Dual chip enable and byte enables (BHE/BLE) support byte writes. Available in 48-pin TSOP I tape and reel.

Features

  • 16-Mbit SRAM; 1M×16 or 2M×8
  • Embedded ECC single-bit correction
  • ERR output flags corrected read errors
  • 45 ns or 55 ns read cycle time
  • OE to data valid: 22 ns (45 ns)
  • Supply: 1.65–2.2 V or 4.5–5.5 V
  • Standby current max 16 µA (5 V)
  • Byte writes via BHE/BLE enables
  • Byte power-down when BHE/BLE high
  • Tri-state I/O when deselected
  • TTL-compatible inputs and outputs
  • Operating temp: –40°C to +85°C

Benefits

  • ECC improves data integrity in SRAM
  • ERR pin simplifies fault monitoring
  • 45/55 ns access supports fast CPUs
  • 22 ns OE timing reduces read wait
  • Dual VCC options ease system reuse
  • 16 µA max standby extends battery
  • Byte write saves bandwidth and power
  • Byte power-down cuts idle current
  • Tri-state outputs simplify bus sharing
  • TTL I/O eases interfacing to logic
  • –40°C to +85°C enables harsh use
  • 16-Mbit density cuts ext memory need
Documents

Design resources

Developer community

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