CY7C15632KV18-500BZXI
Active and preferred
RoHS Compliant
Lead-free

CY7C15632KV18-500BZXI

Datasheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C15632KV18-500BZXI
CY7C15632KV18-500BZXI
Datasheet


Product details

  • Density
    72 MBit
  • Family
    QDR-II+
  • Frequency
    500 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4M x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial

Recommended
OPN
CY7C15632KV18-500BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
CY7C15632KV18-500BZXI is a 72-Mbit QDR II+ synchronous pipelined SRAM (4 M × 18) with independent read and write ports for concurrent transactions and no bus turnarounds. It operates up to 500 MHz with DDR transfers (1,000 MHz data rate), four-word burst, and 2.5-cycle read latency when DOFF is HIGH. VDD is 1.7 V to 1.9 V and VDDQ is 1.4 V to VDD, in a Pb-free 165-ball FBGA for -40 to +85°C.

Features

  • QDR II+ SRAM, 72 Mbit
  • Separate read/write data ports
  • Concurrent read and write access
  • 500 MHz clock operation
  • DDR I/O, 1000 MHz data transfer
  • Four-word burst architecture
  • 2.5-cycle read latency (DOFF=H)
  • Echo clocks CQ/CQ for capture
  • QVLD pin indicates valid data
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • 72 Mbit fits large buffers
  • No bus turnaround, higher BW
  • Parallel R/W cuts contention
  • 500 MHz supports high throughput
  • DDR doubles data rate per clock
  • Burst lowers address bus toggling
  • Predictable latency simplifies timing
  • CQ/CQ eases high-speed capture
  • QVLD reduces read data errors
  • JTAG speeds board test/debug

Applications

Documents

Design resources

Partner solutions

Developer community