CY7C1480BV33-200AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1480BV33-200AXC

Data Sheet
package

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CY7C1480BV33-200AXC
CY7C1480BV33-200AXC
Data Sheet

Product details

  • Architecture
    Standard Sync, Pipeline SCD
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    200 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1480BV33-200AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1480BV33-200AXC is a 72-Mbit pipelined synchronous SRAM organized as 2M × 36 with a 2-bit internal burst counter. It supports 200 MHz bus operation with registered inputs/outputs for 3-1-1-1 burst access, byte writes, and single-cycle chip deselect. The core runs from 3.135 V to 3.6 V (VDD) with 2.5 V or 3.3 V I/O (VDDQ), includes IEEE 1149.1 JTAG, and provides a ZZ sleep mode option.

Features

  • Bus operation up to 250 MHz
  • 3.0 ns max clock-to-output tCO
  • Registered I/O for pipelining
  • High-performance 3-1-1-1 access
  • 2-bit wraparound burst counter
  • Linear or interleaved burst (MODE)
  • ADSP/ADSC address strobes
  • ADV increments burst address
  • Byte write via BWE and BWX
  • Global write (GW) all bytes
  • Asynchronous OE tri-state control
  • ZZ sleep mode with data retention

Benefits

  • 250 MHz supports high throughput
  • 3.0 ns tCO lowers read latency
  • Pipelining boosts system clock rate
  • 3-1-1-1 speeds burst transfers
  • On-chip counter cuts external logic
  • Burst modes fit CPU bus types
  • ADSP/ADSC simplifies bus interfacing
  • ADV enables fast sequential fetches
  • Byte write reduces write bandwidth
  • Global write speeds full updates
  • Tri-state eases bus sharing
  • Sleep mode reduces idle power

Applications

Documents

Design resources

Partner solutions

Developer community

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