CY7C1470V25-200AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1470V25-200AXC

Datasheet
package

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CY7C1470V25-200AXC
CY7C1470V25-200AXC
Datasheet


Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    200 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    2.38 V to 2.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1

Recommended
OPN
CY7C1470V25-200AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 360
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1470V25-200AXC is a 72-Mbit (2M × 36) 2.5 V synchronous pipelined burst SRAM with NoBL architecture, supporting 200 MHz bus operation with zero wait states. It uses registered inputs/outputs, 3 chip enables plus asynchronous OE, and an on-chip burst counter for up to four transfers (linear or interleaved). Byte-write (BWa–BWd) and ZZ sleep mode are supported. Packaged in 100-pin Pb-free TQFP.

Features

  • NoBL SRAM, zero wait-state R/W
  • 200 MHz synchronous pipelined bus
  • Fully registered inputs and outputs
  • 3.0 ns max clock-to-output (tCO)
  • Burst counter: up to 4 transfers
  • Linear or interleaved burst order
  • Byte write with BW[x] selects
  • 2.5 V VDD supply (2.375-2.625 V)
  • 2.5 V VDDQ I/O supply (2.375-VDD)
  • Clock enable (CEN) stalls clock
  • Asynchronous OE for tri-state control
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • No wait states boost bandwidth
  • 200 MHz supports fast SRAM buses
  • Registered I/O eases timing closure
  • 3.0 ns tCO cuts read latency
  • 4-beat bursts reduce addr toggles
  • Burst order fits cache line needs
  • Byte writes simplify RMW updates
  • 2.5 V core lowers power vs 3.3 V
  • 2.5 V I/O matches common logic
  • CEN enables cycle stretching
  • OE prevents bus contention
  • JTAG speeds board test/debug

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