CY7C1069G30-10BVXIT
Active and preferred
RoHS Compliant
Lead-free

CY7C1069G30-10BVXIT

package

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CY7C1069G30-10BVXIT
CY7C1069G30-10BVXIT

Product details

  • Density
    16 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    2M x 8
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns
Recommended
OPN
CY7C1069G30-10BVXIT
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1069G30-10BVXIT is a 16-Mbit (2M × 8) asynchronous CMOS SRAM with embedded ECC for single-bit error correction. The -10 speed grade supports 10 ns access time. It operates from a 2.2 V to 3.6 V supply over the industrial range (−40°C to +85°C) and is offered in a 48-ball VFBGA tape-and-reel package. Automatic CE power-down current is specified up to 30 mA (CMOS inputs) at f = 0.

Features

  • 2M words × 8-bit SRAM array
  • Embedded ECC single-bit correction
  • tAA address access down to 10 ns
  • Read cycle time tRC down to 10 ns
  • OE to data valid tDOE down to 5 ns
  • Data retention at VCC = 1.0 V
  • ICC 90 mA typ at 100 MHz
  • ISB2 20 mA typ power-down
  • Dual chip enable inputs (CE1, CE2)
  • High-Z outputs when deselected
  • TTL-compatible inputs and outputs
  • > 2001 V ESD (MIL-STD-883)

Benefits

  • Corrects single-bit RAM soft errors
  • Simplifies error monitoring via ERR
  • 10 ns access supports fast CPUs
  • 5 ns OE enables quick bus reads
  • 10 ns tRC boosts read throughput
  • 1.0 V retention cuts backup power
  • Lower supply current at 100 MHz
  • Power-down current reduces idle draw
  • Dual CE enables flexible memory decode
  • High-Z outputs ease bus sharing
  • TTL I/O levels reduce glue logic
  • High ESD improves handling robustness

Applications

Documents

Design resources

Partner solutions

Developer community

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