CY7C1051H30-10ZSXE
Active and preferred
RoHS Compliant
Lead-free

CY7C1051H30-10ZSXE

Datasheet
package

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CY7C1051H30-10ZSXE
CY7C1051H30-10ZSXE
Datasheet


Product details

  • Alarms
    N
  • Density
    8 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 125 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Automotive
  • Real Time Clock
    N
  • Speed
    10 ns
  • Watchdog Timer
    N

Recommended
OPN
CY7C1051H30-10ZSXE
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1350
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1350
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
CY7C1051H30-10ZSXE is an AEC-Q100 qualified 8-Mbit (512K × 16) fast asynchronous CMOS SRAM with embedded ECC. It operates from 2.2 V to 3.6 V over -40°C to 125°C, with 10 ns access time and up to 160 mA operating ICC. Automatic CE power-down reduces standby to 50 mA (ISB2), and 1.0 V data retention is supported. The device uses TTL-compatible I/O and comes in a Pb-free 44-pin TSOP II package.

Features

  • 8-Mbit (512K × 16) SRAM
  • Embedded ECC encoder/decoder
  • 10 ns read and write cycle time
  • 5 ns OE to data valid (tDOE)
  • 2.2 V to 3.6 V VCC supply
  • -40°C to +125°C ambient range
  • Automatic CE power-down mode
  • 1.0 V data retention (VDR)
  • ICC max 160 mA at fMAX
  • Input/output leakage ±5 µA
  • 10 pF max CIN/COUT
  • TTL-compatible I/O levels

Benefits

  • 8 Mbit stores larger code/data
  • ECC improves data integrity
  • 10 ns cycles cut memory latency
  • 5 ns OE access speeds reads
  • 2.2–3.6 V fits common rails
  • -40 to +125°C suits harsh use
  • CE power-down reduces idle power
  • 1.0 V retention preserves data
  • Max 160 mA eases power sizing
  • ±5 µA leakage cuts standby loss
  • 10 pF loads support fast buses
  • TTL levels simplify interfacing

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