CY62165E-3XWI
Active and preferred
RoHS Compliant
Lead-free

CY62165E-3XWI

Datasheet

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CY62165E-3XWI
CY62165E-3XWI
Datasheet


Product details

  • Density
    16 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    None
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    5.5 V
  • Operating Voltage range
    1.65 V to 5.5 V
  • Organization (X x Y)
    x8 / x16
  • Page Access Time
    45 ns
  • Qualification
    Industrial
  • Speed
    0 ns

Recommended
OPN
CY62165E-3XWI
Product Status active and preferred
Infineon Package --
Package Name N/A
Packing Size 1
Packing Type WAFER UNSAWN
Moisture Level N/A
Moisture Packing NON DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package --
Package Name -
Packing Size 1
Packing Type WAFER UNSAWN
Moisture Level -
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Diffusion (CoD)
US
CY62165E-3XWI is a 16-Mbit MoBL static RAM die supplied as known-good die (KGD3) in wafer form (XW, 25–30 mil). It supports 1 M × 16 or 2 M × 8 organizations selected by pad connections, with x16 bus width in the ordering code. The device targets industrial temperature grade and includes standard SRAM controls such as CE, WE, and byte enables (BHEB/BLEB in x16 mode) for embedded memory designs.

Features

  • 16-Mbit SRAM (1M×16 or 2M×8)
  • BYTEB selects ×16 or ×8 bus
  • Upper I/O8–I/O15 in ×16 only
  • SA pad adds address for 2M×8
  • WE and OE are active-low controls
  • CE1 is active-low chip enable
  • CE2 is active-high chip enable
  • VCCQ/VSSQ tied to VCC/VSS
  • All VCC pads shorted on die
  • All VSS pads shorted on die
  • DNU pads must be left floating
  • Bond ≥1 VCC/VSS per side

Benefits

  • Choose ×16 or ×8 for bus fit
  • BYTEB strap avoids glue logic
  • ×8 mode cuts bonded I/O needs
  • SA enables larger ×8 addressing
  • Active-low WE/OE eases design-in
  • Dual CE pins simplify decoding
  • I/O rails ease system interfacing
  • Shorted VCC/VSS lowers IR drop
  • Many supply pads boost integrity
  • DNU rules reduce damage risk
  • Bonding rules prevent rework
  • Pad map speeds die integration

Applications

Documents

Design resources

Partner solutions

Developer community