CY62147EV30LL-45BVXI
Active and preferred
RoHS Compliant
Lead-free

CY62147EV30LL-45BVXI

Datasheet
package
ea.
in stock

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CY62147EV30LL-45BVXI
CY62147EV30LL-45BVXI
ea.
Datasheet


Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial

Recommended
OPN
CY62147EV30LL-45BVXI
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 4800
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 4800
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY62147EV30LL-45BVXI is a 4-Mbit (256K × 16) high-performance CMOS SRAM for battery-powered embedded systems. It operates from 2.2 V to 3.6 V over -40°C to +85°C and provides 45 ns access time. Ultra-low power includes 3.5 mA typ active current at 1 MHz and 2.5 µA typ standby with automatic CE power-down and byte enables (BHE/BLE). It is supplied in a Pb-free 48-ball VFBGA package.

Features

  • 256K × 16 SRAM organization
  • 45 ns read/write cycle time
  • 2.2 V to 3.6 V single supply
  • 3.5 mA active at 1 MHz typ
  • 2.5 µA standby current typ
  • 1.5 V data-retention VCC
  • 8.8 µA data-retention max
  • Auto power-down on deselect
  • Byte writes via BHE/BLE
  • Tri-state outputs with OE
  • ±1 µA input/output leakage
  • > 2001 V ESD (MIL-STD-883)

Benefits

  • 16-bit SRAM fits buffer needs
  • 45 ns supports fast CPU access
  • 2.2–3.6 V fits 3 V rails
  • Low active current cuts power
  • µA standby extends battery life
  • Retain data at 1.5 V backup
  • Low ICCDR eases hold-up design
  • Power-down saves energy when idle
  • Byte write reduces bus traffic
  • Tri-state enables easy bus sharing
  • Low leakage aids low-power designs
  • High ESD improves robustness

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Design resources

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