CY62146G-45ZSXA
Active and preferred
RoHS Compliant
Lead-free

CY62146G-45ZSXA

Datasheet
package

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CY62146G-45ZSXA
CY62146G-45ZSXA
Datasheet

Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    5.5 V
  • Operating Voltage range
    4.5 V to 5.5 V
  • Organization (X x Y)
    256Kb x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Automotive(A)
  • Speed
    45 ns
Recommended
OPN
CY62146G-45ZSXA
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1350
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1350
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62146G-45ZSXA is a 4-Mbit (256K × 16) asynchronous SRAM with embedded ECC for single-bit error correction. It targets Automotive-A systems (-40°C to +85°C) with AEC-Q100 qualification and supports 45 ns access time. The device operates from 4.5 V to 5.5 V VCC, has automatic power-down standby current of 3.5 µA typical, and supports byte-wide access via BHE/BLE in a Pb-free 44-pin TSOP II (ZS) package.

Features

  • 4-Mbit SRAM, 256K x 16
  • Embedded ECC 1-bit correction
  • 45 ns read cycle time (tRC)
  • 45 ns addr-to-data valid (tAA)
  • 22 ns OE low to data valid
  • 45 ns write cycle time (tWC)
  • 35 ns WE pulse width (tPWE)
  • Typical standby current 3.5 µA
  • Typ ICC 15 mA at fMAX
  • Data retention at 1.0 V (VDR)
  • Data retention current 13 µA max
  • Input/output leakage ±1 µA max

Benefits

  • Improves data integrity with ECC
  • Higher throughput with 16-bit bus
  • Fast reads with 45 ns cycle time
  • Lower read latency with 22 ns OE
  • Fast writes with 45 ns write cycle
  • Cuts idle power with 3.5 µA standby
  • Keeps data at 1.0 V during backup
  • Low retention current saves energy
  • Low leakage reduces power loss
  • Easier troubleshooting of bit errors
  • Simple async SRAM interface timing
  • Supports shared buses via Hi-Z

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