CY62138FV30LL-45BVXIT
Active and preferred
RoHS Compliant
Lead-free

CY62138FV30LL-45BVXIT

Datasheet
package

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CY62138FV30LL-45BVXIT
CY62138FV30LL-45BVXIT
Datasheet


Product details

  • Density
    2 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 8
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial

Recommended
OPN
CY62138FV30LL-45BVXIT
Product Status active and preferred
Infineon Package
PG-VFBGA-36
Package Name VFBGA-36 (51-85149)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-VFBGA-36
Package Name VFBGA-36 (51-85149)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62138FV30LL-45BVXIT is a 2-Mbit (256 K × 8) CMOS static RAM with 45 ns access time for fast random read/write storage. It operates from 2.2 V to 3.6 V over –40°C to 85°C and uses CE1/CE2 plus OE/WE control, with automatic power-down when deselected. Supply current is 1.6 mA typ at 1 MHz (2.5 mA max) and standby current is 1 µA typ (5 µA max). It is a Pb-free 36-ball VFBGA device.

Features

  • 2-Mbit SRAM, 256K × 8
  • 45 ns read/write cycle time
  • VCC range 2.2 V to 3.6 V
  • ICC 1.6 mA typ at 1 MHz
  • Standby 1 µA typ, 5 µA max
  • Auto power-down when deselected
  • Data retention at VCC = 1.5 V
  • ICCDR 4 µA max at VCC = 1.5 V
  • 18-bit address bus (A0 to A17)
  • 8-bit bidirectional I/O (I/O0–I/O7)
  • Dual chip enables CE1 and CE2
  • High-Z outputs when deselected

Benefits

  • Fits 8-bit MCU data bus
  • 45 ns supports fast CPU access
  • 2.2–3.6 V matches 3 V rails
  • Low active ICC reduces energy
  • µA standby extends battery life
  • Auto power-down saves idle power
  • 1.5 V retention keeps data in sleep
  • Low ICCDR cuts retention drain
  • 18-bit addr eases memory mapping
  • High-Z outputs prevent bus fights
  • Dual CE and OE simplify expansion
  • Async SRAM interface speeds design

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