S27KS0643GABHB023
not for new design
RoHS Compliant
Lead-free

S27KS0643GABHB023

Datasheet
package

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S27KS0643GABHB023
S27KS0643GABHB023
Datasheet


Product details

  • Density
    64 MBit
  • Family
    KS-3
  • Initial Access Time
    35 ns
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    xSPI (Octal)
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Automotive
  • Technology
    HYPERRAM

OPN
S27KS0643GABHB023
Product Status not for new design
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes

Product Status not for new design
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
S27KS0643GABHB023 is a 64 Mb HYPERRAM™ self-refresh DRAM (PSRAM) with an Octal xSPI interface and 8-bit DQ bus plus RWDS. It supports 1.8 V-only operation (VCC 1.7 V to 2.0 V), DDR transfers up to 200 MHz clock and 400 MB/s throughput, with 35 ns max access time. Power modes include hybrid sleep and deep power down down to 12 µA. It is AEC-Q100 Grade 2 (-40°C to 105°C) in 24-ball FBGA.

Features

  • Octal xSPI with CS# and RWDS
  • 8-bit DQ data bus
  • 1.8 V and 3.0 V interface
  • 200 MHz maximum clock rate
  • DDR transfers on both edges
  • Up to 400 MBps data throughput
  • Burst modes: linear and wrapped
  • Wrap bursts: 16/32/64/128 B
  • Hybrid burst: wrap then linear
  • Configurable output drive strength
  • Hybrid Sleep retains memory data
  • Deep power down stops refresh

Benefits

  • Octal xSPI reduces routing effort
  • RWDS strobe simplifies DDR design
  • Dual-voltage I/O fits more MCUs
  • 200 MHz supports fast memory access
  • DDR boosts bandwidth per clock
  • 400 MBps enables high-speed buffers
  • Burst modes tune system efficiency
  • Wrapped bursts reduce bus overhead
  • Hybrid burst aids mixed access
  • Drive strength tuning improves SI
  • Hybrid Sleep saves power, keeps data
  • DPD cuts current in idle states
Documents

Design resources

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