CY7S1049G30-10VXI
Active and preferred
RoHS Compliant
Lead-free

CY7S1049G30-10VXI

Data Sheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7S1049G30-10VXI
CY7S1049G30-10VXI
Data Sheet

Product details

  • Density
    4 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    512K x 8
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns
Recommended
OPN
CY7S1049G30-10VXI
Product Status active and preferred
Infineon Package
PG-SOJ-36
Package Name SOJ-36 (51-85090)
Packing Size 475
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-SOJ-36
Package Name SOJ-36 (51-85090)
Packing Size 475
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7S1049G30-10VXI is a 4-Mbit (512K × 8) fast asynchronous SRAM with PowerSnooze™ Deep-Sleep and embedded ECC for single-bit error correction. It supports 10 ns access at 2.2 V to 3.6 V over -40°C to +85°C. Deep-Sleep current is 15 µA max; CMOS standby (ISB2) is 8 mA max; active ICC is 45 mA max. Device uses CE/OE/WE control and DS pin for low-power retention, in a Pb-free 36-pin SOJ.

Features

  • 4-Mbit SRAM, 512K × 8 org
  • 10 ns / 15 ns address access
  • Read cycle time tRC 10/15 ns
  • OE to data valid tDOE 4.5/8 ns
  • Embedded ECC corrects 1-bit errors
  • Deep-Sleep current IDS max 15 µA
  • DS to Deep-Sleep tDS max 1 ms
  • Wake to access tDSCA 300 µs
  • Data retention at VDR = 1.0 V
  • TTL-compatible inputs and outputs
  • Operating temp –40°C to +85°C

Benefits

  • Fast reads reduce memory latency
  • Quick OE timing speeds bus turns
  • ECC reduces silent data corruption
  • 15 µA Deep-Sleep cuts power draw
  • DS pin enables on-demand sleep
  • 300 µs wake supports fast resume
  • 1.0 V retention saves backup power
  • TTL levels ease legacy interfaces
  • –40°C to +85°C improves robustness
  • Predictable timing eases design

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }