CY62147G30-45ZSXIT
Active and preferred
RoHS Compliant
Lead-free

CY62147G30-45ZSXIT

Datasheet
package
ea.
in stock

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CY62147G30-45ZSXIT
CY62147G30-45ZSXIT
ea.
Datasheet


Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    45 ns

Recommended
OPN
CY62147G30-45ZSXIT
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
PH
Country of Diffusion (CoD)
TW
ea.
in stock
CY62147G30-45ZSXIT is a 4-Mbit (256K × 16) asynchronous CMOS SRAM with embedded ECC for single-bit error correction. It operates at 2.2 V to 3.6 V over -40°C to 85°C and supports 45 ns access. Automatic power-down cuts standby to 3.5 µA typical (8.7 µA max). ICC is 15 mA typical (20 mA max) at fmax. Byte enables (BLE/BHE) support upper/lower byte access. 44-pin TSOP II, tape-and-reel.

Features

  • 4-Mbit SRAM, 256K × 16
  • Embedded ECC 1-bit correction
  • 45 ns/55 ns read cycle time tRC
  • 16-bit I/O with BLE/BHE byte en
  • HI-Z outputs when deselected
  • Standby current max 8.7 µA
  • Data retention VDR = 1.0 V
  • ICCDR max 13 µA at VCC = 1.2 V
  • Operating temp –40°C to +85°C
  • ESD >2001 V (MIL-STD-883)
  • Latch-up current >140 mA

Benefits

  • ECC corrects single-bit faults
  • 45/55 ns enables fast access
  • Byte enables cut write activity
  • HI-Z outputs ease bus sharing
  • 8.7 µA max standby saves power
  • 1.0 V retention preserves data
  • 13 µA retention cuts backup load
  • –40°C to +85°C boosts reliability
  • >2001 V ESD improves handling
  • >140 mA latch-up adds robustness
  • Async SRAM avoids DRAM refresh

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