CY62126EV30LL-45ZSXAT
Active and preferred
RoHS Compliant
Lead-free

CY62126EV30LL-45ZSXAT

Datasheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY62126EV30LL-45ZSXAT
CY62126EV30LL-45ZSXAT
Datasheet


Product details

  • Density
    1 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn;Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    64K x 16
  • Peak Reflow Temp
    260 °C
  • Qualification
    Automotive
  • Speed
    45 ns

Recommended
OPN
CY62126EV30LL-45ZSXAT
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
CY62126EV30LL-45ZSXAT is a 1-Mbit (64 K × 16) CMOS static RAM with 45 ns access time, optimized for low-power portable and automotive designs. It operates from 2.2 V to 3.6 V and supports automatic power-down when addresses are not toggling. Standby current is 4 µA max with CE HIGH, and active current is 2.0 mA max at 1 MHz. Operating range is -40°C to +85°C. It is offered in a Pb-free 44-pin TSOP II package.

Features

  • 1-Mbit SRAM organized as 64K × 16
  • 45 ns read/write cycle time
  • 2.2 V to 3.6 V single-supply VCC
  • 1.3 mA typ active at 1 MHz
  • 4 µA max standby current
  • Auto power-down when addr static
  • Data retention at VCC down to 1.5 V
  • 3 µA max data-retention current
  • Byte write via BLE/BHE controls
  • Tri-state I/O via CE/OE/BHE/BLE

Benefits

  • 16-bit bus cuts MCU accesses
  • 45 ns suits fast SRAM interfaces
  • 2.2–3.6 V fits 3 V systems
  • Low active current extends runtime
  • µA standby minimizes sleep drain
  • Auto power-down saves idle power
  • 1.5 V retain data in deep sleep
  • Low ICCDR reduces backup load
  • Byte writes reduce write energy
  • Tri-state eases bus sharing/expand
Documents

Design resources

Partner solutions

Developer community