CY7C1059H30-10ZSXIT
Active and preferred
RoHS Compliant
Lead-free

CY7C1059H30-10ZSXIT

Additional technical information
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1059H30-10ZSXIT
CY7C1059H30-10ZSXIT
Additional technical information

Product details

  • Density
    8 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    1M x 8
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
Recommended
OPN
CY7C1059H30-10ZSXIT
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1059H30-10ZSXIT is an 8-Mbit (1M × 8) asynchronous CMOS SRAM with embedded ECC for single-bit error correction. It operates from 2.2 V to 3.6 V over -40°C to 85°C and offers 10 ns address access (tAA). Dual chip enables (CE1/CE2) control read/write via OE and WE, and I/Os tri-state when deselected. Typical ICC is 90 mA at 100 MHz with ISB2 20 mA standby. It is offered in a Pb-free 44-pin TSOP II (ZS) package.

Features

  • 8-Mbit SRAM (1M words x 8)
  • Embedded ECC, single-bit correct
  • 2.2 V to 3.6 V VCC range
  • 1.0 V data retention mode
  • tAA 10 ns access time
  • 10 ns read cycle time (tRC)
  • 10 ns write cycle time (tWC)
  • OE to data valid 5 ns (tDOE)
  • Dual chip enable (CE1, CE2)
  • Tri-state outputs (OE/CE/WE)
  • TTL-compatible I/O thresholds
  • ERR output flags 1-bit ECC event

Benefits

  • ECC corrects 1-bit memory errors
  • ERR pin enables fault monitoring
  • 10 ns cycles support fast buses
  • 5 ns OE latency speeds reads
  • 2.2-3.6 V fits 3.3 V rails
  • 1.0 V retention saves backup power
  • Dual CE eases memory chip select
  • Tri-state I/Os simplify bus sharing
  • TTL I/O simplifies interfacing logic
  • ±1 µA I/O leakage reduces loss
  • CE power-down cuts standby current
  • High-speed SRAM cuts wait states

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }