Active and preferred
RoHS Compliant

IQE046N08LM5CGSC

OptiMOS™ 5 power MOSFET 80 V logic level in PQFN 3.3x3.3 Source-Down Center-Gate DSC package
Data Sheet
package

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IQE046N08LM5CGSC
IQE046N08LM5CGSC
Data Sheet

Product details

  • Budgetary Price €/1k
    1.28
  • ID (@25°C) max
    99 A
  • IDpuls max
    396 A
  • Operating Temperature range
    -55 °C to 175 °C
  • Package
    PQFN 3.3x3.3 Source-Down
  • Polarity
    N
  • Ptot max
    100 W
  • QG (typ @4.5V)
    19 nC
  • QG (typ @10V)
    38 nC
  • RDS (on) (@10V) max
    4.6 mΩ
  • RDS (on) (@4.5V) max
    5.9 mΩ
  • Special Features
    Logic Level, Center-Gate Dual-Side Cooling
  • VDS max
    80 V
  • VGS(th) range
    1.1 V to 2.3 V
  • VGS(th)
    1.7 V
Recommended
OPN
IQE046N08LM5CGSCATMA1
Product Status active and preferred
Infineon Package
PG-WHTFN-9
Package Name PQFN 3.3x3.3 Source-Down DSC
Packing Size 6000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-WHTFN-9
Package Name PQFN 3.3x3.3 Source-Down DSC
Packing Size 6000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
IQE046N08LM5CGSC is Infineon’s new best-in-class OptiMOS™ 5 power MOSFET 80 V logic level in PQFN 3.3x3.3 Source-Down Center-Gate (CG) dual-side cooling (DSC) package, offering the industry’s lowest on-state resistance RDS(on) at 25˚C , superior thermal performance, and optimized parallelization. The OptiMOS™ Source-Down is a revolutionary design with a flipped silicon die inside, which offers several advantages, such as increased thermal capability, advanced power density and improved layout possibilities. Combined with the innovative dual-side cooling package, which can dissipate up to three times more power than the traditional overmolded package, IQE046N08LM5CGSC is targeted for high power density and performance SMPS products commonly found in telecom and data servers

Features

  • Logic level allows lower Qrr and QOSS
  • Reduced RDS(on) by up to 30% compared 
  • Improved RthJC over current PQFN
  • New, optimized layout possibilities
  • Center Gate optimized for paralleling

Benefits

  • Enabling highest power density
  • Superior thermal performance
  • Efficient layout for space use
  • Simplified MOSFET parallelization

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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