CY7C1650KV18-450BZC
Active and preferred

CY7C1650KV18-450BZC

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CY7C1650KV18-450BZC
CY7C1650KV18-450BZC
Datasheet

Product details

  • Architecture
    DDR-II+ CIO
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    N
  • Family
    DDR-II+ CIO
  • Frequency
    450 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    2
Recommended
OPN
CY7C1650KV18-450BZC
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1650KV18-450BZC is a 144-Mbit DDR II+ synchronous pipelined SRAM organized as 4 M × 36 with two-word burst. It supports 450 MHz maximum clock and DDR data transfers at 900 MHz, with 2.0-cycle read latency (or 1 cycle when DOFF is low). Core VDD is 1.7 V to 1.9 V and I/O VDDQ is 1.4 V to VDD. It includes CQ/CQ echo clocks, QVLD data-valid, ZQ impedance match, and IEEE 1149.1 JTAG.

Features

  • 144-Mbit DDR II+ pipelined SRAM
  • 450 MHz clock, 900 MHz DDR data
  • Two-word burst architecture
  • Read latency 2 cycles (DOFF high)
  • DDR I mode: 1-cycle latency (DOFF)
  • Dual input clocks K and K
  • Echo clocks CQ/CQ
  • QVLD valid-data indicator
  • ZQ pin for programmable impedance
  • RQ 175–350 Ω impedance match range
  • PLL runs 120 MHz to max clock
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • High bandwidth for fast memories
  • DDR boosts throughput per clock
  • Two-word burst lowers addr toggling
  • 2-cycle latency for stable timing
  • DDR I mode eases system bring-up
  • K/K improves DDR timing margin
  • CQ/CQ simplifies high-speed capture
  • QVLD reduces read timing guesswork
  • ZQ matching reduces signal ringing
  • Wide RQ supports common line Z0
  • PLL improves data placement at speed
  • JTAG speeds board test and debug

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