CY7C1481BV33-133BGXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1481BV33-133BGXI

Data Sheet
package

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CY7C1481BV33-133BGXI
CY7C1481BV33-133BGXI
Data Sheet

Product details

  • Architecture
    Standard Sync, Flow-through
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    133 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1481BV33-133BGXI
Product Status active and preferred
Infineon Package
PG-BGA-119
Package Name FBGA-119 (51-85181)
Packing Size 84
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-119
Package Name FBGA-119 (51-85181)
Packing Size 84
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1481BV33-133BGXI is a 72-Mbit (2M × 36) synchronous flow-through SRAM for high-speed microprocessor interfaces. It supports 133 MHz operation with 6.5 ns clock-to-data access and a 2-bit on-chip burst counter for linear or interleaved 2-1-1-1 bursts. Core supply is 3.135 V to 3.6 V with 2.375 V to 3.6 V I/O, and it includes IEEE 1149.1 JTAG and a ZZ sleep mode for –40°C to +85°C operation.

Features

  • 133 MHz synchronous bus operation
  • 6.5 ns max tCDV from clock rise
  • 2M × 36 common I/O architecture
  • 2-bit on-chip burst counter
  • Linear or interleaved burst via MODE
  • High-performance 2-1-1-1 access rate
  • Separate ADSP and ADSC strobes
  • Byte writes via BWx plus BWE
  • Global write (GW) writes all bytes
  • Asynchronous OE for tri-state control
  • ZZ sleep mode, 2-cycle entry/exit
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • 133 MHz supports fast cache SRAM
  • 6.5 ns reduces read latency
  • 36-bit I/O fits wide data paths
  • Burst counter cuts address overhead
  • Select burst order per CPU needs
  • 2-1-1-1 boosts sustained bandwidth
  • ADSP/ADSC simplify bus control
  • Byte writes reduce data toggling
  • Global write eases full-word writes
  • Async OE enables shared data bus
  • Sleep mode lowers standby current
  • JTAG speeds board test and debug

Applications

Documents

Design resources

Partner solutions

Developer community

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