CY62167EV18LL-55BVI
Active and preferred

CY62167EV18LL-55BVI

Datasheet
package
ea.
in stock

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CY62167EV18LL-55BVI
CY62167EV18LL-55BVI
ea.
Datasheet


Product details

  • Density
    16 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.65 V to 2.25 V
  • Organization (X x Y)
    1M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial

Recommended
OPN
CY62167EV18LL-55BVI
Product Status active and preferred
Infineon Package
P-VFBGA-48
Package Name BGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
P-VFBGA-48
Package Name BGA-48 (51-85150)
Packing Size 960
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Est. Longevity Date 2033
Launch Date 03/2022
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
US
ea.
in stock
CY62167EV18LL-55BVI is a 16-Mbit (1 M × 16) CMOS SRAM with 55 ns access for asynchronous read/write. It operates from 1.65 V to 2.25 V over -40°C to +85°C and uses automatic power-down when deselected (CE1/CE2) to cut standby to 1.5 µA typical (12 µA max). Active ICC is 2.2 mA typical at 1 MHz (4.0 mA max), and operating ICC is 25 mA typical at fmax. The x16 bus supports byte writes via BHE/BLE.

Features

  • 1 M × 16 CMOS SRAM array
  • 55 ns read/write cycle time
  • 1.65 V to 2.25 V VCC operation
  • 1.5 µA typ standby current
  • 12 µA max standby current
  • 2.2 mA typ ICC at 1 MHz
  • 30 mA max ICC at fmax
  • OE/CE tri-state outputs (High-Z)
  • Byte write via BHE/BLE signals
  • 10 pF max CIN/COUT
  • ESD >2001 V (MIL-STD-883)
  • -40°C to +85°C ambient range

Benefits

  • Fits 16-bit buses, fewer chips
  • 55 ns supports fast SRAM access
  • Low VCC suits low-voltage SoCs
  • µA standby extends battery life
  • Low max standby improves sleep power
  • Low active mA cuts runtime power
  • 30 mA max bounds supply sizing
  • High-Z outputs simplify bus sharing
  • Byte writes reduce write bandwidth
  • Low capacitance eases signal timing
  • ESD robustness improves handling yield
  • Wide temp range improves reliability

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