CY62146G30-45ZSXI
Active and preferred
RoHS Compliant
Lead-free

CY62146G30-45ZSXI

Datasheet
package
ea.
in stock

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CY62146G30-45ZSXI
CY62146G30-45ZSXI
ea.
Datasheet

Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    45 ns
Recommended
OPN
CY62146G30-45ZSXI
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 675
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 675
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY62146G30-45ZSXI is a 4-Mbit (256K × 16) asynchronous CMOS SRAM with embedded ECC for single-bit error correction. The -45 speed grade supports 45 ns access at 2.2 V–3.6 V over the industrial range (-40°C to +85°C). It is offered in a 44-pin TSOP II package (ZS) with single chip enable, supports byte writes via BLE/BHE, and reduces standby power with ISB2 of 3.5 µA typ (8.7 µA max).

Features

  • 4-Mbit SRAM (256K × 16)
  • Embedded ECC single-bit correct
  • 45 ns or 55 ns read cycle
  • OE access 22 ns (45 ns grade)
  • 16-bit I/O with byte enables
  • Address bus A0-A17 (18 bits)
  • Single or dual chip enable inputs
  • Auto power-down standby 3.5 µA typ
  • Standby current 8.7 µA max
  • 1.0-V data retention mode
  • TTL-compatible I/O levels
  • Outputs go HI-Z when deselected

Benefits

  • Fits 16-bit memory maps easily
  • ECC corrects bit errors on read
  • 45 ns supports fast CPU access
  • 22 ns OE enables low read latency
  • Byte writes reduce bus bandwidth
  • 18-bit address simplifies decode
  • Flexible CE options ease design-in
  • µA standby extends battery life
  • Low max standby eases power budget
  • Retention saves data in deep sleep
  • TTL I/O eases logic interfacing
  • HI-Z outputs simplify bus sharing
Documents

Design resources

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