Active and preferred
RoHS Compliant
Lead-free

S25FS512SAGBHM213

Data Sheet
package
software

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S25FS512SAGBHM213
S25FS512SAGBHM213
Data Sheet

Product details

  • Classification
    ISO 26262-ready
  • Density
    512 MBit
  • Family
    FS-S
  • Interface Bandwidth
    66 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / -
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature
    -40 °C to 125 °C
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Automotive
Recommended
OPN
S25FS512SAGBHM213
Product Status active and preferred
Infineon Package
PG-TFBGA-24
Package Name FBGA-24 (002-15534)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TFBGA-24
Package Name FBGA-24 (002-15534)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S25FS512SAGBHM213 is a 512 Mb (64 MB) automotive-grade SPI NOR Flash memory with 65-nm MIRRORBIT™ technology and Eclipse architecture for fast program and erase. It supports SPI Multi-I/O, single/dual/quad data lines, up to 133 MHz SDR and 80 MHz DDR, and operates from 1.7 V to 2.0 V. Qualified to AEC-Q100 Grade 1 (-40°C to +125°C), it offers 100,000 program-erase cycles and 20-year data retention. Ideal for automotive and embedded code storage and fast data access.

Features

  • SPI interface with multi-I/O support
  • Supports clock modes 0 and 3
  • Double data rate (DDR) option
  • 24- or 32-bit addressing
  • Compatible command set with S25FL families
  • Multiple read modes: Normal, Fast, Dual
  • Burst wrap, continuous (XIP), QPI modes
  • 256/512-byte page programming buffer
  • Internal ECC with single bit correction
  • Hybrid and uniform sector erase options
  • 100,000 program-erase cycles minimum
  • 20 year data retention minimum

Benefits

  • Flexible I/O enables faster data transfer
  • DDR option boosts throughput
  • Large page buffer increases programming speed
  • ECC improves data reliability
  • Multiple erase options suit varied designs
  • High endurance for long device life
  • Long data retention secures information
  • Low voltage reduces power consumption
  • Deep power-down saves energy
  • OTP array enhances system security
  • Advanced protection prevents unauthorized
  • Compatible with existing designs

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }