Active and preferred
RoHS Compliant
Lead-free

S28HS02GTFPBHB050

Data Sheet
package

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S28HS02GTFPBHB050
S28HS02GTFPBHB050
Data Sheet

Product details

  • Classification
    ISO 26262-compliant
  • Density
    2 GBit
  • Family
    HS-T
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    Octal
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature
    -40 °C to 105 °C
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Qualification
    Automotive
Recommended
OPN
S28HS02GTFPBHB050
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S28HS02GTFPBHB050 is a 2 Gb SEMPER™ NOR Flash memory utilizing Infineon's 45-nm MIRRORBIT™ technology in a dual-die package. It supports octal and SPI interfaces, delivers up to 400 MBps read rates in DDR mode, and operates at 1.8 V. Safety features include ISO26262 ASIL B compliance, ECC (SECDED), SafeBoot, and Endurance flex architecture. Sector and block protection plus CRC-based data integrity ensure robust operation in automotive and industrial environments.

Features

  • Embedded Hamming ECC for error correction
  • 16-byte data unit with 1-bit correction,
  • ECC error reporting via status registers
  • Endurance flex architecture with wear
  • Configurable high endurance or long retention
  • JEDEC JESD251 xSPI compliant interface
  • Supports Octal and legacy SPI interfaces
  • SDR and DDR modes for high-speed access
  • Flexible sector architecture: 4 KB and 256 KB
  • Page programming buffer: 256 or 512 bytes
  • Data integrity check with CRC
  • SafeBoot for initialization and corruption

Benefits

  • ECC improves data reliability and safety
  • 2-bit error detection prevents data
  • Status registers enable fast diagnostics
  • Wear leveling extends device lifetime
  • Flexible endurance/retention for various
  • xSPI compliance ensures broad compatibility
  • Octal/SPI support eases system integration
  • High-speed modes boost data throughput
  • Flexible sectors fit diverse memory maps
  • Large buffer increases programming speed
  • CRC checks enhance data integrity
  • SafeBoot ensures secure startup

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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