S28HS02GTFPBHB050
Active and preferred
RoHS Compliant
Lead-free

S28HS02GTFPBHB050

Data Sheet
package

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S28HS02GTFPBHB050
S28HS02GTFPBHB050
Data Sheet

Product details

  • Classification
    ISO 26262-compliant
  • Density
    2 GBit
  • Family
    HS-T
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    Octal
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Qualification
    Automotive
Recommended
OPN
S28HS02GTFPBHB050
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
S28HS02GTFPBHB050 is a 2 Gbit SEMPER™ NOR Flash MCP for automotive code and data storage over an Octal interface. It operates from 1.7 V to 2.0 V across -40°C to 105°C and supports Octal DDR up to 166 MHz (333 MByte/s). ISO 26262-compliant features include SECDED ECC, SafeBoot diagnostics, data-integrity CRC, endurance flex wear leveling, and advanced sector protection. RoHS compliant and halogen free.

Features

  • MIRRORBIT™ stores 2 bits per cell
  • Dual-die MCP (DDP) architecture
  • Uniform or hybrid sector architecture
  • 4 KB and 256 KB sector options
  • 256 or 512-byte program buffer
  • 1024-byte OTP secure silicon array
  • JESD251 xSPI compliant interface
  • Octal SDR/DDR with DS data strobe
  • Hamming ECC per 16-byte data unit
  • SECDED: correct 1-bit, detect 2-bit
  • ECC status, trap addr, INT# alert
  • SafeBoot failure signature status

Benefits

  • Higher density in same die size
  • More memory in one MCP footprint
  • Tune sectors for code and data
  • 4 KB erase reduces update time
  • Faster programming improves throughput
  • OTP helps protect keys and IDs
  • JEDEC xSPI eases host integration
  • DS simplifies high-speed reads
  • ECC improves read data reliability
  • 2-bit detect avoids silent faults
  • INT# enables quick error response
  • SafeBoot aids recovery after faults

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }