CY7C4121KV13-633FCXI
Active and preferred
RoHS Compliant
Lead-free

CY7C4121KV13-633FCXI

Data Sheet
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CY7C4121KV13-633FCXI
CY7C4121KV13-633FCXI
Data Sheet

Product details

  • Architecture
    QDR-IV
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 18
  • Density
    144 MBit
  • ECC
    Y
  • Family
    QDR-IV
  • Frequency
    633 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.26 V to 1.34 V
  • Organization (X x Y)
    8Mb x 18
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Industrial
  • Read Latency (Cycles)
    5
Recommended
OPN
CY7C4121KV13-633FCXI
Product Status active and preferred
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 120
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 120
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C4121KV13-633FCXI is a 144-Mbit QDR-IV HP SRAM organized as 8M × 18 with dual independent bidirectional DDR data ports and a shared DDR address bus. It supports a 2-word burst, 633 MHz max clock (1266 MT/s RTR), read latency 5 cycles and write latency 3 cycles. It runs from 1.3 V core with HSTL/SSTL or POD I/O, includes on-die termination, optional address parity, and on-chip ECC for single-bit correction.

Features

  • 144-Mbit QDR-IV HP SRAM
  • Total rate 1334 MT/s
  • Max operating freq 667 MHz
  • Read latency 5 clock cycles
  • Write latency 3 clock cycles
  • Two-word burst on all accesses
  • Dual bidirectional DDR data ports
  • Concurrent read/write on both ports
  • DDR address, SDR control signaling
  • POD, HSTL, SSTL I/O (JESD)
  • On-die termination, programmable
  • ECC, bus inversion, address parity

Benefits

  • 144 Mbit reduces external memory
  • 1334 MT/s boosts throughput
  • 667 MHz supports fast clocks
  • 5-cycle reads cut wait states
  • 3-cycle writes reduce latency
  • Two-word burst improves efficiency
  • Dual ports increase concurrency
  • Full-duplex access reduces stalls
  • DDR address enables high RTR
  • JESD I/O eases board interfacing
  • ODT simplifies signal integrity
  • ECC/parity reduces data corruption

Applications

Documents

Design resources

Partner solutions

Developer community

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