CY7C4042KV13-933FCXC
Active and preferred
RoHS Compliant
Lead-free

CY7C4042KV13-933FCXC

Data Sheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C4042KV13-933FCXC
CY7C4042KV13-933FCXC
Data Sheet

Product details

  • Architecture
    QDR-IV
  • Bank Switching
    Y
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    Y
  • Family
    QDR-IV
  • Frequency
    933 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.26 V to 1.34 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    8
Recommended
OPN
CY7C4042KV13-933FCXC
Product Status active and preferred
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C4042KV13-933FCXC is a 72-Mbit QDR-IV XP SRAM in a 2M × 36 organization with dual independent bidirectional DDR data ports and a single DDR address bus. The 933 speed grade supports up to 933 MHz (1866 MT/s) with two-word bursts, 8-bank architecture (one access per bank per cycle), and fixed read latency 8 cycles and write latency 5 cycles. It uses 1.3 V VDD and is offered in a 361-ball Pb-free FCBGA.

Features

  • 72-Mbit synchronous SRAM
  • 2132 MT/s random transaction rate
  • 1066 MHz max operating frequency
  • Read latency: 8 clock cycles
  • Write latency: 5 clock cycles
  • Dual bidirectional DDR data ports
  • DDR address, SDR control signaling
  • 8 internal banks, 1 access/bank
  • Two-word burst on all accesses
  • On-die termination (ODT)
  • Address and data bus inversion
  • On-chip ECC + address parity

Benefits

  • Handles high-bandwidth workloads
  • Enables 1066 MHz high-speed access
  • Predictable 8-cycle read timing
  • Short write latency reduces stalls
  • Full-duplex read/write bandwidth
  • Shared addr bus simplifies routing
  • Banking sustains parallel accesses
  • Burst-2 improves bus efficiency
  • ODT improves signal integrity
  • Bus inversion cuts SSN and EMI
  • ECC improves data reliability
  • Parity helps catch addr faults

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }