CY7C2665KV18-450BZXI
Active and preferred
RoHS Compliant

CY7C2665KV18-450BZXI

Data Sheet
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CY7C2665KV18-450BZXI
CY7C2665KV18-450BZXI
Data Sheet

Product details

  • Architecture
    QDR-II+, ODT
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II+, ODT
  • Frequency
    450 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2.5
Recommended
OPN
CY7C2665KV18-450BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C2665KV18-450BZXI is a 144-Mbit QDR II+ synchronous pipelined SRAM organized as 4M × 36 with separate read and write ports for concurrent transactions. It supports a 450 MHz clock with DDR transfers (900 MT/s) and four-word burst operation with 2.5-cycle read latency (1-cycle in QDR I mode via DOFF). 1.8 V core supply and on-die termination for D/BWS and K/K inputs simplify high-speed board design.

Features

  • QDR II+ SRAM, 4-word burst
  • 550 MHz clock, 1100 MHz DDR data
  • Separate read/write data ports
  • Supports concurrent transactions
  • 2.5-cycle read latency (DOFF=1)
  • 1-cycle read latency mode (DOFF=0)
  • On-die termination for D/BWS/K
  • Echo clocks (CQ/CQ) for capture
  • QVLD pin indicates valid output data
  • PLL locks with 20 µs stable clock
  • PLL operates down to 120 MHz
  • VDD 1.7–1.9 V; VDDQ 1.4 V–VDD

Benefits

  • High bandwidth with fewer addresses
  • Faster transfers at 1100 MHz DDR
  • No bus turnarounds, lower latency
  • Read+write same time boosts throughput
  • Predictable 2.5-cycle read timing
  • 1-cycle reads cut access delay
  • ODT reduces external termination BOM
  • CQ/CQ eases timing at high speed
  • QVLD simplifies receive data capture
  • PLL stabilizes data placement
  • Runs PLL even at 120 MHz clocks
  • Works with 1.4 V or 1.5 V I/O

Applications

Documents

Design resources

Partner solutions

Developer community

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