CY7C1515KV18-300BZCT
Active and preferred

CY7C1515KV18-300BZCT

Data Sheet
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CY7C1515KV18-300BZCT
CY7C1515KV18-300BZCT
Data Sheet

Product details

  • Architecture
    QDR-II
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    QDR-II
  • Frequency
    300 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1.5
Recommended
OPN
CY7C1515KV18-300BZCT
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1515KV18-300BZCT is a 72-Mbit QDR II synchronous pipelined SRAM (2M × 36) with independent read/write ports and a four-word burst architecture. It supports DDR transfers on both ports at up to 300 MHz clock, uses K/K input clocks and C/C output clocks with echo CQ/CQ, and offers 1.5-cycle read latency with DOFF HIGH (1-cycle QDR I mode with DOFF LOW). Core VDD is 1.8 V ±0.1 V with 1.4 V to VDD I/O VDDQ.

Features

  • Separate read/write data ports
  • 333 MHz clock, 666 MHz DDR data
  • Four-word burst per access
  • 1.5-cycle read latency (DOFF=H)
  • 1-cycle read latency (DOFF=L)
  • K/K and C/C differential clocks
  • Echo clocks CQ/CQ for capture
  • Multiplexed address for both ports
  • Byte write via BWS inputs
  • Programmable output impedance (ZQ)
  • PLL operates 120 MHz to fMAX
  • VDD 1.7–1.9 V, VDDQ 1.4–VDD

Benefits

  • No bus turnaround, less contention
  • Higher bandwidth at 333 MHz
  • Fewer address toggles, lower EMI
  • Predictable latency for pipelines
  • QDR I compatible timing option
  • Improved DDR timing margins
  • Simplifies high-speed data capture
  • Fewer pins, simpler PCB routing
  • Enables read-modify-write updates
  • Better signal integrity matching
  • Accurate data placement vs skew
  • Supports 1.8 V core, 1.5 V I/O

Applications

Documents

Design resources

Partner solutions

Developer community

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