CY7C1480BV33-250BZI
Active and preferred

CY7C1480BV33-250BZI

Data Sheet
package
ea.
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CY7C1480BV33-250BZI
CY7C1480BV33-250BZI
ea.
Data Sheet

Product details

  • Architecture
    Standard Sync, Pipeline SCD
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    220 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1480BV33-250BZI
Product Status active and preferred
Infineon Package
P -BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant No
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
P -BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C1480BV33-250BZI is a 72-Mbit pipelined synchronous SRAM organized as 2M × 36. It uses registered inputs/outputs and a 2-bit internal burst counter to support 3-1-1-1 accesses with user-selectable linear or interleaved sequences. It operates from 3.135 V to 3.6 V VDD with 2.5 V or 3.3 V VDDQ I/O, and supports bus clocks up to 250 MHz (3.0 ns access) in a 165-ball FBGA industrial package.

Features

  • Bus operation up to 250 MHz
  • 3.0 ns max clock-to-output tCO
  • Registered I/O for pipelining
  • High-performance 3-1-1-1 access
  • 2-bit wraparound burst counter
  • Linear or interleaved burst (MODE)
  • ADSP/ADSC address strobes
  • ADV increments burst address
  • Byte write via BWE and BWX
  • Global write (GW) all bytes
  • Asynchronous OE tri-state control
  • ZZ sleep mode with data retention

Benefits

  • 250 MHz supports high throughput
  • 3.0 ns tCO lowers read latency
  • Pipelining boosts system clock rate
  • 3-1-1-1 speeds burst transfers
  • On-chip counter cuts external logic
  • Burst modes fit CPU bus types
  • ADSP/ADSC simplifies bus interfacing
  • ADV enables fast sequential fetches
  • Byte write reduces write bandwidth
  • Global write speeds full updates
  • Tri-state eases bus sharing
  • Sleep mode reduces idle power

Applications

Documents

Design resources

Partner solutions

Developer community

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