Active and preferred
RoHS Compliant

S70KL1283DPBHV020

Data Sheet
package
ea.
in stock

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S70KL1283DPBHV020
S70KL1283DPBHV020
ea.
Data Sheet

Product details

  • Density
    128 MBit
  • Family
    KL-3
  • Initial Access Time
    36 ns
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    xSPI (Octal)
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM
Recommended
OPN
S70KL1283DPBHV020
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S70KL1283DPBHV020 is a 128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) with an Octal xSPI DDR interface and 8-bit data bus plus RWDS and RESET#. It supports 3.0 V VCC/VCCQ and up to 166 MHz clock (DP speed grade), with tACC 35 ns. Self-managed refresh inserts extra initial latency when needed, and Hybrid Sleep and Deep Power Down reduce standby power for embedded memory expansion.

Features

  • Octal xSPI interface
  • 1.7 V to 2.0 V VCC/VCCQ
  • 2.7 V to 3.6 V VCC/VCCQ
  • 200 MHz maximum clock rate
  • DDR on both clock edges
  • Throughput up to 400 MBps
  • 8-bit DQ[7:0] data bus
  • RWDS strobe and write data mask
  • Optional differential clock CK/CK#
  • Optional DCARS read strobe
  • Linear and wrapped burst modes
  • Hybrid Sleep and Deep Power Down

Benefits

  • Octal DDR boosts system bandwidth
  • 400 MBps supports fast frame buffers
  • 200 MHz fits high-speed controllers
  • 8-bit bus reduces signal routing
  • RWDS eases DDR timing margins
  • DCARS improves DDR read eye margin
  • Wrapped bursts reduce access latency
  • Burst modes match cache or streaming
  • Sleep/DPD lowers standby power
  • Partial refresh cuts idle refresh power
  • Dual-voltage fits 1.8 V or 3.0 V rails
  • RESET# enables quick fault recovery

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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