Active and preferred
RoHS Compliant
Lead-free

S26KL256SDABHB023

Data Sheet
package
software

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S26KL256SDABHB023
S26KL256SDABHB023
Data Sheet

Product details

  • Bus Width
    x8
  • Classification
    ISO 26262-ready
  • Density
    256 MBit
  • Family
    KL-S
  • Initial Access Time
    96 ns
  • Interface Bandwidth
    200 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 100
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Automotive
  • Technology
    HYPERFLASH
Recommended
OPN
S26KL256SDABHB023
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S26KL256SDABHB023 is a 256 Mb (32 MB) HYPERFLASH™ memory for embedded systems, featuring HYPERBUS™ interface with 3.0 V operation and up to 100 MHz clock rate. It delivers sustained read throughput up to 200 MBps, supports DDR transfers, and offers 96 ns initial access time. Uniform 256 KB sectors, ECC (1-bit correction, 2-bit detection), CRC, and advanced protection ensure robust data integrity. Automotive-grade options meet AEC-Q100 standards.

Features

  • 3.0 V I/O with 11 bus signals
  • 1.8 V I/O with 12 bus signals
  • Up to 333 MBps sustained read throughput
  • DDR: two data transfers per clock
  • 8-bit data bus (DQ[7:0])
  • 96-ns initial random read access time
  • 512-byte program buffer
  • ECC: 1-bit correction, 2-bit detection
  • Hardware accelerated CRC calculation
  • Secure silicon region (1024-byte OTP)
  • Advanced sector protection methods
  • Low power modes: standby 25 µA, deep

Benefits

  • High throughput enables fast data access
  • DDR boosts system performance
  • 8-bit bus simplifies integration
  • Fast random access reduces latency
  • Large buffer speeds up programming
  • ECC ensures reliable data integrity
  • CRC detects data errors quickly
  • Secure region protects critical data
  • Flexible sector protection enhances security
  • Low power modes extend battery life

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Documents

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Developer community

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