S26HS512TGABHI000
Active and preferred
RoHS Compliant
Lead-free

S26HS512TGABHI000

Data Sheet
package
ea.
in stock

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S26HS512TGABHI000
S26HS512TGABHI000
ea.
Data Sheet

Product details

  • Density
    512 MBit
  • Family
    HS-T
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Qualification
    Industrial
Recommended
OPN
S26HS512TGABHI000
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S26HS512TGABHI000 is a 512 Mbit SEMPER™ NOR flash in the HS-T family with a HYPERBUS™ interface. It runs from 1.7 V to 2.0 V across -40°C to 85°C (industrial) and supports DDR operation at 200 MHz for up to 400 MByte/s reads. Integrated ECC (SECDED), interface CRC, and data integrity CRC support robust error handling, and advanced sector protection and OTP SSR help secure firmware.

Features

  • 45-nm MIRRORBIT™ 2 bits per cell
  • HYPERBUS™ DDR read up to 400 MBps
  • JEDEC JESD251 xSPI compatible
  • Data strobe (DS) for read capture
  • Default boot: x1 SPI or x8 HYPERBUS
  • 256 KB uniform or hybrid sectors
  • 256/512-byte page program buffer
  • Embedded ECC on 16-byte data unit
  • SECDED: correct 1-bit, detect 2-bit
  • ECC reporting: INT#, counter, trap
  • Advanced sector protect: DYB/PPB
  • Password-lockable nonvolatile protect

Benefits

  • Higher density per die area
  • Fast execute-in-place reads
  • Simpler JEDEC-based host design
  • More margin at high-speed reads
  • Flexible boot across host modes
  • Optimize erase granularity per use
  • Faster program with fewer writes
  • Automatic correction of bit flips
  • Early detection of double-bit faults
  • Easier ECC fault logging and debug
  • Prevents accidental erase/program
  • Locks protection settings securely

Applications

Documents

Design resources

Partner solutions

Developer community

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