TRAVEO™ T2G CYT3DL

• Supports 2D and 2.5D (perspective warping, 3D effects) graphics rendering.
• Internal colour resolution
• 2048 KB of embedded video RAM memory (VRAM)
• Two video output interfaces supporting a display from
  • Parallel RGB (max display size: 1600 × 600 at 80 MHz)
  • FPD-link single (max display size: 1920 × 720 at 110 MHz)
• One Capture engine for video input processing for ITU 656 or parallel RGB/YUV or MIPI CSI-2 input
• Display warping on-the-fly for HUD applications
• Direct video feed through from capture to display interface with graphics overlay
• Composition engine for scene composition from display layers
• Display engine for video timing generation and display functions
• Drawing engine for acceleration of vector graphics rendering
• Command sequencer for setup and control of the rendering process
• Supports graphics rendering without frame buffers (on-the-fly)
• Single-channel FPD-Link/LVDS interface for up to HD resolution video output

• Four time-division multiplexing (TDM) interfaces
• Two pulse-code modulation-pulse width modulation (PCM-PWM) interfaces
• Up to five sound generator (SG) interfaces
• Two PCM Audio stream mixers with five input streams
• One audio digital-to-analog converter (DAC)

240-MHz (max) 32-bit Arm^® Cortex^®-M7 CPUs, with

• Single-cycle multiply
• Single/double-precision floating point unit (FPU)
• 16-KB data cache, 16-KB instruction cache
• Memory protection unit (MPU)
• 64-KB instruction and 64-KB data Tightly-Coupled Memories (TCM)

100-MHz 32-bit Arm^® Cortex^®-M0+ CPU with

• Single-cycle multiply
• Memory protection unit

Inter-processor communication in hardware

4 DMA controllers

• 4160-KB code-flash with an additional 128-KB of work-flash
• 384-KB of SRAM with selectable retention granularity

• Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
• Secure boot and authentication
• AES: 128-bit blocks, 128-/192-/256-bit keys
• 3DES: 64-bit blocks, 64-bit key
• Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve (ECC)
• SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data
• CRC: supports CCITT CRC16 and IEEE-802.3 CRC32
• True random number generator (TRNG) and pseudo random number generator (PRNG)
• Galois/Counter Mode (GCM)

• Memory protection unit (MPU)
• Shared memory protection unit (SMPU)
• Peripheral protection unit (PPU)
• Watchdog timer (WDT)
• Multi-counter watchdog timer (MCWDT)
• Low-voltage detector (LVD)
• Brown-out detection (BOD)
• Over-voltage detection (OVD)
• Overcurrent detection (OCD)
• Clock supervisor (CSV)
• Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)

• Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power management
• Configurable options for robust BOD

• Up to four pins to wakeup from Hibernate mode
• Up to 61 GPIO pins to wakeup from DeepSleep mode
• Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes

• Internal main oscillator (IMO)
• Internal low-speed oscillator (ILO)
• External crystal oscillator (ECO)
• Watch crystal oscillator (WCO)
• Phase-locked loop (PLL)
• Frequency-locked loop (FLL)
• Low-power external crystal oscillator (LPECO)

• Up to four CAN FD channels
• Up to 12 runtime-reconfigurable SCB (serial communication block) channels, each configurable as I²C, SPI, or UART
• Up to two independent LIN channels
• Up to two CXPI channels with data rate up to 20 kbps
• 10/100 Mbps Ethernet MAC interface conforming to IEEE-802.3bw

• Two SPIs (single, dual, quad, or octal), xSPI interface
• On-the-fly encryption and decryption
• Execute-In-Place (XIP) from external memory

• Up to 50 16-bit and 32 32-bit Timer/Counter Pulse-Width modulator (TCPWM) blocks for regular operations
• Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep

• Year/Month/Date, Day-of-week, Hour:Minute:Second fields
• 12- and 24-hour formats
• Automatic leap-year correction

• Up to 135 programmable I/Os
• Four I/O types
  • GPIO Standard (GPIO_STD)
  • GPIO Enhanced (GPIO_ENH)
  • GPIO Stepper Motor Control (GPIO_SMC)
  • High-Speed I/O Standard with Low Noise (HSIO_STDLN)

• Regulators
• PMIC control module

• One SAR A/D converter
• The ADC also supports six internal analog inputs like
  • Bandgap reference to establish absolute voltage levels
  • Calibrated diode for junction temperature calculations
  • Two AMUXBUS inputs and two direct connections to monitor supply levels
• ADC supports addressing of external multiplexers
• ADC has a sequencer supporting autonomous scanning of configured channels

• One smart I/O block, which can perform Boolean operations on signals going to and from I/Os
• Up to eight I/Os (GPIO_STD) supported

• JTAG controller and interface compliant to IEEE-1149.1-2001
• Arm^® SWD (serial wire debug) port
• Supports Arm^® Embedded Trace Macrocell (ETM) Trace 

• GHS MULTI or IAR EWARM for code development and debugging

• 272-BGA, 16 × 16 × 1.7 mm (max), 0.8-mm ball pitch
• 216-TEQFP, 24 × 24 × 1.6 mm (max), 0.4-mm ball pitch
• 208-TEQFP, 28 × 28 × 30 mm (max), 0.5-mm ball pitch

• Direct memory access (or DMA) is a key technology that enables efficient data transfer and management without CPU involvement

• Become familiar with the transfer modes of the DMA and get to know some basic DMA use cases

•Know the features of the Inter-Processor Communication (IPC)
•Gain knowledge on basic use cases of the Inter-Processor Communication (IPC)

• Define MCU companions, list the challenges they address and describe some use cases
• Know about Infineon’s automotive MCUs 

Watch eLearning

• Understand the evolution of the cockpit architecture
• Recognize the importance of the central modules like head unit and cockpit domain controllers and get to know Infineon solutions and their components

Wacth eLearning

• Be aware of the Ethernet’s interface basic operations on AURIX™ TC3xx and TRAVEO™ T2G
• Identify which time-sensitive networking (TSN) features are supported by both generations’ derivatives

Watch eLearning

• Identify common security threats to modern cars
• Understand how OPTIGA™ TPM can help automotive systems achieve a high level of security and their applications in different use cases in various host environments

Watch eLearning

• Describe the main features of Infineon’s TRAVEO™ T2G microcontrollers
• Recognize the different variants that make up this family of products

Watch eLearning

• Infineon has a successful history of supporting various graphics applications in cars with displays.
• Infineon's TRAVEO™ T2G microcontrollers are designed to meet size constraints, reduce costs, and improve performance and bandwidth for car displays, compared to system-on-chip solutions.

Watch eLearning

In this training, you will get to know the TRAVEO™ T2G portfolio for body and graphics applications, its key features and safety functions, development kits, and finally TRAVEO™’s automotive software and tool partner ecosystem.

Watch eLearning

TRAVEO™ T2G protection units provide robust security and protection against malicious or unintended access.

With TRAVEO™ T2G fault subsystem it is possible to detect and diagnose faults in microcontroller systems.