Active and preferred
RoHS Compliant
Lead-free

S80KS2563GABHI023

Data Sheet
package

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S80KS2563GABHI023
S80KS2563GABHI023
Data Sheet

Product details

  • Density
    256 MBit
  • Family
    KS-3
  • Initial Access Time
    35 ns
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    xSPI (Octal)
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM
Recommended
OPN
S80KS2563GABHI023
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S80KS2563GABHI023 is a 256 Mb HYPERRAM™ self-refresh DRAM with an Octal xSPI DDR interface for low-latency memory expansion. It supports up to 200 MHz clock and 400 MBps (3,200 Mbps) throughput, with 35 ns maximum access time. It operates from 1.7 V to 2.0 V, includes hybrid sleep and deep power-down, and is supplied in a 24-ball FBGA; this I-grade option is rated -40°C to 85°C.

Features

  • Octal xSPI interface, DDR
  • 200 MHz maximum clock rate
  • Up to 400 MBps (3,200 Mbps)
  • 8-bit data bus DQ[7:0]
  • RWDS strobe and write data mask
  • Optional diff clock CK/CK#
  • Hardware reset pin RESET#
  • Linear or wrapped burst 16-128 B
  • Hybrid burst: wrapped then linear
  • Hybrid sleep retains memory data
  • Deep power down stops all refresh
  • 1.7 V to 2.0 V VCC supply

Benefits

  • DDR octal cuts pin count vs 16-bit
  • 400 MBps speeds memory bandwidth
  • 200 MHz supports fast xSPI hosts
  • RWDS improves DDR timing margin
  • Diff clock improves signal integrity
  • RESET# enables robust recovery
  • Burst options optimize bus efficiency
  • Hybrid burst fits cacheline fetches
  • Hybrid sleep lowers power, keeps data
  • Deep power down minimizes standby I
  • Low VCC reduces system power
  • ESD ratings improve handling margin

Documents

Documents

Design resources

Partner solutions

Developer community

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