Active and preferred
RoHS Compliant
Lead-free

S29GL064S70TFI060

Data Sheet
package
software
ea.
in stock

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S29GL064S70TFI060
S29GL064S70TFI060
ea.
Data Sheet

Product details

  • Density
    64 MBit
  • Family
    GL-S
  • Initial Access Time
    70 ns
  • Interface Frequency (SDR/DDR) (MHz)
    NA
  • Interfaces
    Parallel
  • Lead Ball Finish
    Matte Tin Plating
  • Operating Temperature
    -40 °C to 85 °C
  • Operating Voltage
    3 V
  • Page Access Time
    15 ns
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
Recommended
OPN
S29GL064S70TFI060
Product Status active and preferred
Infineon Package
PG-TSOP-48
Package Name TSOP-48 (51-85183)
Packing Size 480
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-48
Package Name TSOP-48 (51-85183)
Packing Size 480
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S29GL064S70TFI060 is a 64 Mb (8 MB) parallel flash memory based on Infineon's MIRRORBIT™ technology and 65-nm process. Operating from a single 3.0 V supply with versatile I/O (VIO: 1.65 V to VCC), it supports access times down to 70 ns and page read times of 15 ns. Sector protection, hardware ECC, and 100,000 erase cycles per sector ensure reliability. Available in TSOP and BGA packages, it meets industrial and automotive AEC-Q100 Grade 2/3 standards.

Features

  • 3.0 V single power supply operation
  • 65-nm MIRRORBIT™ process technology
  • 16-bit or 8/16-bit data bus options
  • 70 ns access time, 15 ns page read time
  • 8-word/16-byte page read buffer
  • 128-word/256-byte write buffer
  • Internal hardware ECC, single bit correction
  • Advanced sector protection
  • 100,000 erase cycles per sector min
  • 20-year data retention typical
  • Automatic sleep and standby modes
  • JEDEC CFI and command set compatible

Benefits

  • 3.0 V simplifies power design
  • 65-nm tech ensures high reliability
  • Flexible bus supports legacy and new designs
  • Fast access boosts system performance
  • Page buffer enables quick data reads
  • Write buffer speeds up programming
  • ECC improves data integrity
  • Multi-level protection enhances security
  • High endurance lowers maintenance cost
  • Long retention secures critical data
  • Low-power modes extend battery life
  • JEDEC compatibility eases integration

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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