Active and preferred
RoHS Compliant
Lead-free

S25FS512SAGNFI013

Data Sheet
package
software
ea.
in stock

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S25FS512SAGNFI013
S25FS512SAGNFI013
ea.
Data Sheet

Product details

  • Density
    512 MBit
  • Family
    FS-S
  • Interface Bandwidth
    66 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / -
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Matte Tin Plating
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
Recommended
OPN
S25FS512SAGNFI013
Product Status active and preferred
Infineon Package
PG-WSON-8
Package Name DFN-8 (002-15552)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-WSON-8
Package Name DFN-8 (002-15552)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S25FS512SAGNFI013 is a 512 Mb (64 MB) SPI NOR Flash memory based on 65-nm MIRRORBIT™ technology with Eclipse architecture, supporting 1.7 V to 2.0 V supply. It offers single, dual, and quad SPI, up to 80 MB/s DDR Quad I/O read, and 512-byte page buffers. Advanced security features include OTP, block, and password protection. Qualified to AEC-Q100 Grade 1 (-40°C to +125°C), it is ideal for automotive, industrial, and embedded code storage and XIP applications.

Features

  • SPI interface with multi-I/O support
  • Supports clock modes 0 and 3
  • Double data rate (DDR) option
  • 24- or 32-bit addressing
  • Compatible command set with S25FL families
  • Multiple read modes: Normal, Fast, Dual
  • Burst wrap, continuous (XIP), QPI modes
  • 256/512-byte page programming buffer
  • Internal ECC with single bit correction
  • Hybrid and uniform sector erase options
  • 100,000 program-erase cycles minimum
  • 20 year data retention minimum

Benefits

  • Flexible I/O enables faster data transfer
  • DDR option boosts throughput
  • Large page buffer increases programming speed
  • ECC improves data reliability
  • Multiple erase options suit varied designs
  • High endurance for long device life
  • Long data retention secures information
  • Low voltage reduces power consumption
  • Deep power-down saves energy
  • OTP array enhances system security
  • Advanced protection prevents unauthorized
  • Compatible with existing designs

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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