CY7C25442KV18-333BZI
Active and preferred

CY7C25442KV18-333BZI

Data Sheet
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CY7C25442KV18-333BZI
CY7C25442KV18-333BZI
Data Sheet

Product details

  • Architecture
    QDR-II+, ODT
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    QDR-II+, ODT
  • Frequency
    333 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    Y
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2
Recommended
OPN
CY7C25442KV18-333BZI
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY7C25442KV18-333BZI is a 72-Mbit QDR II+ synchronous pipelined SRAM (2M × 36) with separate read and write ports for concurrent transactions. It runs at 333 MHz with DDR data transfer (666 MHz), supports 2.0-cycle read latency (DOFF HIGH), and integrates on-die termination for D, BWS, and K/K inputs. It is a 165-ball FBGA device and operates from 1.7–1.9 V VDD and 1.4 V–VDD VDDQ over -40 to 85°C.

Features

  • QDR II+ SRAM, 2.0-cycle latency
  • 333 MHz clock, DDR at 666 MHz
  • Separate read and write data ports
  • Two-word burst architecture
  • Two input clocks K and K
  • Echo clocks CQ/CQ for capture
  • QVLD pin flags valid output data
  • ODT for D/BWS/K and K inputs
  • PLL for accurate data placement
  • JTAG IEEE 1149.1 boundary scan
  • VDD 1.7 V to 1.9 V supply
  • VDDQ 1.4 V to VDD supply

Benefits

  • No bus turnaround, higher throughput
  • 333/666 MHz enables high bandwidth
  • Concurrent R/W reduces bottlenecks
  • Burst cuts address bus frequency
  • Dual clocks ease DDR timing closure
  • Echo clocks simplify receiver capture
  • QVLD simplifies timing validation
  • ODT cuts external parts and PCB area
  • PLL improves timing margin and yield
  • JTAG speeds bring-up and debug
  • 1.8 V core lowers system power
  • VDDQ down to 1.4 V saves I/O power

Applications

Documents

Design resources

Partner solutions

Developer community

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