CY7C1665KV18-550BZXC
Active and preferred
RoHS Compliant

CY7C1665KV18-550BZXC

Data Sheet
package

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CY7C1665KV18-550BZXC
CY7C1665KV18-550BZXC
Data Sheet

Product details

  • Architecture
    QDR-II+
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II+
  • Frequency
    550 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    2.5
Recommended
OPN
CY7C1665KV18-550BZXC
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1665KV18-550BZXC is a 144-Mbit (4 M × 36) QDR II+ synchronous pipelined SRAM with separate DDR read and write ports. It supports 550 MHz clock operation (1100 MHz data transfer) with four-word burst and 2.5-cycle read latency (DOFF high), or QDR I mode with 1-cycle latency (DOFF low). It uses 1.8 V core with 1.4 V to VDDQ I/O, echo clocks (CQ/CQ) and QVLD for data capture, plus IEEE 1149.1 JTAG.

Features

  • 550 MHz clock, DDR at 1100 MHz
  • Four-word burst (sequential)
  • Separate read and write data ports
  • Concurrent read/write transactions
  • Read latency 2.5 cycles (DOFF=H)
  • QDR I mode, 1-cycle latency (DOFF=L)
  • Two input clocks K/K for DDR timing
  • Echo clocks CQ/CQ for data capture
  • QVLD data-valid, 0.5-cycle early
  • Programmable output impedance via RQ
  • On-chip PLL locks after 20 µs
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • High bandwidth for fast packets
  • Lower addr bus frequency
  • No I/O bus turnaround delays
  • Read/write same time, less stalls
  • Predictable 2.5-cycle reads
  • Switch to 1-cycle for low latency
  • Easier timing closure at high speed
  • Simpler data capture, less skew
  • Clean valid window for receivers
  • Better signal integrity, fewer SI fixes
  • Accurate data placement after power-up
  • Faster board debug and test access

Applications

Documents

Design resources

Partner solutions

Developer community

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