CY7C1615KV18-300BZXI
Active and preferred
RoHS Compliant

CY7C1615KV18-300BZXI

Data Sheet
package

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CY7C1615KV18-300BZXI
CY7C1615KV18-300BZXI
Data Sheet

Product details

  • Architecture
    QDR-II
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II
  • Frequency
    300 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1.5
Recommended
OPN
CY7C1615KV18-300BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1615KV18-300BZXI is a 144-Mbit QDR II synchronous pipelined SRAM (4 M × 36) with separate read and write ports for concurrent transactions. It supports DDR transfers at 666 MHz using a 333 MHz clock and four-word burst operation, with 1.5-cycle read latency when DOFF is high. It operates over the industrial range (TA −40°C to +85°C) from 1.7–1.9 V VDD and 1.4 V to VDD VDDQ in a 165-ball FBGA.

Features

  • Dual R/W ports, no bus turnaround
  • 333 MHz clock, DDR data at 666 MHz
  • Four-word burst per address
  • 1.5-cycle read latency (DOFF=H)
  • 1-cycle read latency (DOFF=L)
  • Single clock mode (tie C/C HIGH)
  • Echo clocks CQ/CQ for data capture
  • PLL locks after 20 us stable clock
  • ZQ+RQ programmable output impedance
  • Byte write via BWS[x:0]
  • 1.7-1.9 V core; 1.4 V-VDDQ I/O
  • IEEE 1149.1 JTAG test access port

Benefits

  • Eliminates bus turnaround delays
  • High bandwidth with 333 MHz clocks
  • Lower address rate, fewer addr pins
  • Predictable pipeline read timing
  • Optional lower latency QDR I mode
  • Simplifies clocking, less skew risk
  • Echo clocks ease high-speed capture
  • Fast PLL lock speeds system bring-up
  • Impedance match improves signal SI
  • Byte writes avoid read-modify-write
  • Supports 1.5 V or 1.8 V I/O rails
  • Boundary scan speeds PCB test

Applications

Documents

Design resources

Partner solutions

Developer community

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