CY7C1387KV33-167AXC
Active and preferred
RoHS Compliant
Lead-free

CY7C1387KV33-167AXC

Data Sheet
package

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CY7C1387KV33-167AXC
CY7C1387KV33-167AXC
Data Sheet

Product details

  • Architecture
    Standard Sync, Pipeline DCD
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 18
  • Density
    18 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    167 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.135 V to 3.6 V
  • Organization (X x Y)
    1Mb x 18
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    2
Recommended
OPN
CY7C1387KV33-167AXC
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 720
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 720
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1387KV33-167AXC is an 18-Mbit synchronous SRAM (1M × 18) with registered inputs/outputs and pipelined operation for high-speed systems up to 167 MHz. It supports 3-1-1-1 burst reads/writes with a 2-bit on-chip counter and user-selectable linear or interleaved sequences, plus byte writes and synchronous self-timed writes. 3.3 V VDD core and 2.5 V/3.3 V VDDQ I/O, 100-pin Pb-free TQFP, and ZZ sleep mode are included.

Features

  • Bus operation up to 200 MHz
  • 3 ns clock-to-output (200 MHz)
  • 3-1-1-1 burst access rate
  • Registered I/O for pipelining
  • Double-cycle deselect (DCD)
  • Interleaved or linear burst
  • Self-timed synchronous writes
  • Byte write plus global write (GW)
  • Separate ADSP and ADSC strobes
  • Asynchronous output enable (OE)
  • VDD 3.135 V to 3.6 V
  • VDDQ 2.375 V to 2.625 V or VDD

Benefits

  • 200 MHz supports fast datapaths
  • 3 ns reduces read latency
  • 3-1-1-1 improves bandwidth
  • Pipelining eases timing closure
  • DCD enables no-wait expansion
  • Burst options match access patterns
  • Self-timed writes cut control logic
  • Byte writes reduce wasted writes
  • Dual strobes simplify bus sharing
  • Async OE helps bus turn-around
  • 3.3 V core fits common power rails
  • 2.5 V I/O interfaces to low-V SoC

Applications

Documents

Design resources

Partner solutions

Developer community

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