CY621472GN30-45ZSXIT
Active and preferred
RoHS Compliant
Lead-free

CY621472GN30-45ZSXIT

Datasheet
package

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CY621472GN30-45ZSXIT
CY621472GN30-45ZSXIT
Datasheet

Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Operating Voltage (VCCQ) max
    3.6 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    45 ns
Recommended
OPN
CY621472GN30-45ZSXIT
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY621472GN30-45ZSXIT is a 4-Mbit (256K × 16) CMOS low-power SRAM (MoBL) with dual chip enable. It operates from 2.2 V to 3.6 V over -40°C to +85°C and supports 45 ns access time. Standby (automatic power-down) is 3.5 µA typical, 8.7 µA max, and operating ICC is 15 mA typ, 20 mA max at fmax (22.22 MHz). Byte power-down engages when both BLE and BHE are disabled. 44-pin TSOP II tape-and-reel.

Features

  • 4-Mbit SRAM, 256K x 16
  • 45 ns/55 ns access time options
  • 16-bit I/O with byte enables
  • BHE/BLE byte read/write control
  • Single or dual chip-enable inputs
  • OE-controlled data output
  • Tri-state I/O when deselected
  • Byte Power Down via BHE/BLE
  • Standby current typ 3.5 µA
  • Standby current max 8.7 µA
  • Read cycle time 45 ns min
  • Input/output leakage ±1 µA

Benefits

  • Fast reads for low-latency buffers
  • Save energy in standby modes
  • Byte writes reduce bus traffic
  • Power down per byte saves power
  • Flexible CE fits more bus schemes
  • OE timing eases system interfacing
  • HI-Z outputs simplify bus sharing
  • Low leakage cuts battery drain
  • Predictable 45 ns read timing
  • Byte enables simplify 8-bit access
  • Quick power-up with CE assert
  • Short OE-to-data cuts latency

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