PQFN 2x2

OptiMOS™ and StrongIRFET™ low voltage power MOSFETs in 2x2 PQFN (DFN2020) package

anchor

Overview

The ultra-compact PQFN 2 x 2 portfolio is part of Infineon’s vast offering of small-form-factor MOSFETs with low RDS(on)and high switching performance. This family is optimized for efficiency in a small footprint, making it the perfect solution for load switches, low-power DC-DC applications including LED lighting, and wireless charging MOSFETs.

Products

About

Combined with the highest flexibility in PCB layout routing, the outstanding electrical performance and small footprint of only 2x2 mm² further enable best-in-class power density, form factor improvement, and reduced system temperature in end applications. These allow designers to have a more relaxed thermal management, shrinking of the system size, significant space-saving, reduced system costs, and easy-to-design products.

The PQFN 2x2 package is available with both N-Channel Power IR MOSFET and OptiMOS™ MOSFET technologies, offering customers optimum solutions for both general-purpose and high-performance applications. This ultra-compact package combined with outstanding electrical performance enable form factor improvement in end applications.

The gate threshold voltage, VGS(th) is the minimum amount of gate-to-source voltage required to create a conducting path between the source and drain terminals of the power MOSFET. Infineon offers a variety of options for VGS(th):

  •  NL (Normal level): 2 V - 4 V
  •  LL (Logic level): 1 V - 3 V
  •  SLL (Super logic level): 0.5 V - 1 V
     

When to use logic level (LL/SLL) devices:

  •  In low-frequency applications, the MOSFET can be driven directly from a microcontroller, eliminating the need of an external MOSFET driver.
  •  Some systems have limited bus voltages, e.g., 5 V, which require the use of LL/SLL devices.
     

When to use normal level (NL) devices:

  •  In noisy environments, the elevated threshold voltage prevents false turn-on of the MOSFET.
  •  These devices have a lower gate charge and lower RDS(on), and are not typically limited to <= 100 V devices.

Combined with the highest flexibility in PCB layout routing, the outstanding electrical performance and small footprint of only 2x2 mm² further enable best-in-class power density, form factor improvement, and reduced system temperature in end applications. These allow designers to have a more relaxed thermal management, shrinking of the system size, significant space-saving, reduced system costs, and easy-to-design products.

The PQFN 2x2 package is available with both N-Channel Power IR MOSFET and OptiMOS™ MOSFET technologies, offering customers optimum solutions for both general-purpose and high-performance applications. This ultra-compact package combined with outstanding electrical performance enable form factor improvement in end applications.

The gate threshold voltage, VGS(th) is the minimum amount of gate-to-source voltage required to create a conducting path between the source and drain terminals of the power MOSFET. Infineon offers a variety of options for VGS(th):

  •  NL (Normal level): 2 V - 4 V
  •  LL (Logic level): 1 V - 3 V
  •  SLL (Super logic level): 0.5 V - 1 V
     

When to use logic level (LL/SLL) devices:

  •  In low-frequency applications, the MOSFET can be driven directly from a microcontroller, eliminating the need of an external MOSFET driver.
  •  Some systems have limited bus voltages, e.g., 5 V, which require the use of LL/SLL devices.
     

When to use normal level (NL) devices:

  •  In noisy environments, the elevated threshold voltage prevents false turn-on of the MOSFET.
  •  These devices have a lower gate charge and lower RDS(on), and are not typically limited to <= 100 V devices.

Documents

Design resources

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community ", "labelEn" : "Ask the community " }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions ", "labelEn" : "View all discussions " } ] }