Active and preferred
RoHS Compliant

S70KL1282GABHV020

Data Sheet
package
ea.
in stock

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S70KL1282GABHV020
S70KL1282GABHV020
ea.
Data Sheet

Product details

  • Density
    128 MBit
  • Family
    KL-2
  • Initial Access Time
    35 ns
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM
Recommended
OPN
S70KL1282GABHV020
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S70KL1282GABHV020 is a 128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) with a HYPERBUS™ interface. It supports 2.7 V to 3.60 V supply and clocks up to 200 MHz using DDR transfers for up to 400 MBps throughput, with 35 ns maximum access time. Features include RWDS read strobe/write mask, optional DCARS, configurable linear and wrapped bursts, and hybrid sleep or deep power down in a 24-ball FBGA.

Features

  • HYPERBUS interface
  • 1.7 V to 2.0 V VCC option
  • 2.7 V to 3.60 V VCC option
  • 8-bit DDR data bus (DQ[7:0])
  • 200 MHz maximum clock rate
  • Up to 400 MBps throughput
  • 35 ns maximum access time (tACC)
  • Wrapped bursts 16/32/64/128 B
  • RWDS strobe and write data mask
  • DCARS option shifts RWDS phase
  • Hybrid sleep retains data
  • Deep power down stops refresh

Benefits

  • High bandwidth with few pins
  • Fits 1.8 V or 3.0 V logic rails
  • DDR bus reduces system pin count
  • 200 MHz supports fast processors
  • 400 MBps feeds high-rate buffers
  • 35 ns tACC reduces read latency
  • Burst sizes match cache-line needs
  • RWDS eases DDR timing closure
  • DCARS improves read eye margin
  • Hybrid sleep cuts power, keeps data
  • DPD minimizes leakage when off
  • Clock-stop lowers stall current

Documents

Documents

Design resources

Partner solutions

Developer community

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