Active and preferred
RoHS Compliant
Lead-free

S26KS128SDPBHI020

Data Sheet
package
software
ea.
in stock

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S26KS128SDPBHI020
S26KS128SDPBHI020
ea.
Data Sheet

Product details

  • Bus Width
    x8
  • Density
    128 MBit
  • Family
    KS-S
  • Initial Access Time
    96 ns
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature
    -40 °C to 85 °C
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Industrial
  • Technology
    HYPERFLASH
Recommended
OPN
S26KS128SDPBHI020
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 338
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S26KS128SDPBHI020 is a 128 Mb (16 MB) HYPERFLASH™ memory with HYPERBUS™ interface, supporting 1.8 V and 3.0 V operation. It achieves up to 166 MHz (333 MBps) at 1.8 V and 100 MHz (200 MBps) at 3.0 V, with DDR data transfer and 96 ns initial random read access. Features include advanced sector protection, ECC, CRC, low power modes (standby 25 µA, deep power-down 8 µA), and endurance of 100,000 cycles. Operating temperature ranges from -40°C to +125°C (AEC-Q100 Grade 1).

Features

  • 3.0 V I/O with 11 bus signals
  • 1.8 V I/O with 12 bus signals
  • Up to 333 MBps sustained read throughput
  • DDR: two data transfers per clock
  • 8-bit data bus (DQ[7:0])
  • 96-ns initial random read access time
  • 512-byte program buffer
  • ECC: 1-bit correction, 2-bit detection
  • Hardware accelerated CRC calculation
  • Secure silicon region (1024-byte OTP)
  • Advanced sector protection methods
  • Low power modes: standby 25 µA, deep

Benefits

  • High throughput enables fast data access
  • DDR boosts system performance
  • 8-bit bus simplifies integration
  • Fast random access reduces latency
  • Large buffer speeds up programming
  • ECC ensures reliable data integrity
  • CRC detects data errors quickly
  • Secure region protects critical data
  • Flexible sector protection enhances security
  • Low power modes extend battery life

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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