Active and preferred
RoHS Compliant
Lead-free

S25FS512SAGNFM010

Data Sheet
package
software

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S25FS512SAGNFM010
S25FS512SAGNFM010
Data Sheet

Product details

  • Classification
    ISO 26262-ready
  • Density
    512 MBit
  • Family
    FS-S
  • Interface Bandwidth
    66 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / -
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Matte Tin Plating
  • Operating Temperature
    -40 °C to 125 °C
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Automotive
Recommended
OPN
S25FS512SAGNFM010
Product Status active and preferred
Infineon Package
PG-WSON-8
Package Name DFN-8 (002-15552)
Packing Size 1690
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-WSON-8
Package Name DFN-8 (002-15552)
Packing Size 1690
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S25FS512SAGNFM010 is a 512 Mb (64 MB) NOR flash memory with SPI interface supporting single, dual, and quad I/O, plus DDR reads up to 133 MHz. Built on 65-nm MIRRORBIT™ technology, it features a 512-byte page buffer, 20-year data retention, and operates from 1.7 V to 2.0 V. Qualified to AEC-Q100 Grade 1 (-40°C to +125°C), it offers hybrid/uniform sector options, advanced security, and is ideal for code shadowing, XIP, and data storage in automotive and embedded systems.

Features

  • SPI interface with multi-I/O support
  • Supports clock modes 0 and 3
  • Double data rate (DDR) option
  • 24- or 32-bit addressing
  • Compatible command set with S25FL families
  • Multiple read modes: Normal, Fast, Dual
  • Burst wrap, continuous (XIP), QPI modes
  • 256/512-byte page programming buffer
  • Internal ECC with single bit correction
  • Hybrid and uniform sector erase options
  • 100,000 program-erase cycles minimum
  • 20 year data retention minimum

Benefits

  • Flexible I/O enables faster data transfer
  • DDR option boosts throughput
  • Large page buffer increases programming speed
  • ECC improves data reliability
  • Multiple erase options suit varied designs
  • High endurance for long device life
  • Long data retention secures information
  • Low voltage reduces power consumption
  • Deep power-down saves energy
  • OTP array enhances system security
  • Advanced protection prevents unauthorized
  • Compatible with existing designs

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }