Active and preferred
RoHS Compliant
Lead-free

S25FL512SDSBHBC10

Data Sheet
package
software

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S25FL512SDSBHBC10
S25FL512SDSBHBC10
Data Sheet

Product details

  • Classification
    ISO 26262-ready
  • Density
    512 MBit
  • Family
    FL-S
  • Interface Bandwidth
    80 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / 80
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Automotive
Recommended
OPN
S25FL512SDSBHBC10
Product Status active and preferred
Infineon Package
PG-TFBGA-24
Package Name FBGA-24 (002-15534)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TFBGA-24
Package Name FBGA-24 (002-15534)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S25FL512SDSBHBC10 is a 512 Mb (64 MB) SPI NOR flash memory utilizing Infineon's 65 nm MIRRORBIT™ technology and Eclipse™ architecture for high-speed program and erase. It supports single, dual, and quad SPI Multi-I/O, DDR commands, 2.7 V to 3.6 V core, and 1.65 V to 3.6 V I/O supply. Features include a 512-byte page buffer, uniform 256 KB sectors, advanced sector protection, and AEC-Q100 automotive qualification, ideal for code shadowing, XIP, and automotive data storage.

Features

  • CMOS 3.0 V core with versatile I/O
  • SPI interface with multi I/O support
  • 512 Mb (64 MB) density
  • Supports SPI clock up to 133 MHz
  • Quad, dual, and DDR read commands
  • 512-byte page programming buffer
  • Automatic ECC with single bit correction
  • Uniform 256-KB sectors
  • 100,000 program-erase cycles minimum
  • 20-year data retention minimum
  • 1024-byte OTP secure region
  • Block and advanced sector protection

Benefits

  • Versatile I/O enables flexible system design
  • Multi I/O SPI boosts data throughput
  • High density supports large code/data storage
  • 133 MHz SPI enables fast data access
  • Quad/DDR read maximizes read speed
  • Large buffer speeds up programming
  • ECC improves data reliability
  • Uniform sectors simplify memory management
  • High endurance for long device lifetime
  • 20-year retention ensures data safety
  • OTP region adds security options
  • Advanced protection enhances data safety

Documents

Documents

Design resources

Partner solutions

Developer community

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