CY7C2642KV18-333BZXC
Active and preferred
RoHS Compliant

CY7C2642KV18-333BZXC

Data Sheet
package

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CY7C2642KV18-333BZXC
CY7C2642KV18-333BZXC
Data Sheet

Product details

  • Architecture
    QDR-II+, ODT
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 18
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II+, ODT
  • Frequency
    333 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    8Mb x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    2
Recommended
OPN
CY7C2642KV18-333BZXC
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C2642KV18-333BZXC is a 144-Mbit QDR II+ synchronous pipelined SRAM (8 M × 18) with separate read and write ports for concurrent transactions. It supports 333 MHz operation with DDR interfaces on both ports (666 MHz data rate) and 2.0-cycle read latency. Supplies are 1.7–1.9 V VDD and 1.4 V to VDD I/O (VDDQ). It comes in a 165-ball Pb-free FBGA package for commercial temperature range.

Features

  • QDR II+ two-word burst arch
  • 2.0-cycle read latency (DOFF Hi)
  • 333 MHz clock; 666 MHz DDR data
  • Independent read and write ports
  • Concurrent read/write transactions
  • ODT on D, BWS, and K/K inputs
  • Programmable output impedance (RQ)
  • Echo clocks (CQ/CQ) for capture
  • QVLD data-valid output indicator
  • PLL locks at frequencies to 120 MHz
  • Core VDD 1.8 V ±0.1 V
  • VDDQ 1.4 V to VDD; VREF 0.68 V

Benefits

  • No bus turnaround, higher throughput
  • Burst lowers address bus frequency
  • 666 MHz DDR enables high bandwidth
  • Separate ports avoid R/W contention
  • Concurrency boosts system efficiency
  • ODT cuts external resistor BOM
  • Programmable RQ improves signal
  • Echo clocks ease timing closure
  • QVLD simplifies valid-data capture
  • PLL improves data placement margin
  • 1.8 V core reduces power per bit
  • Lower VDDQ can cut I/O power

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }