CY7C25632KV18-500BZXC
Active and preferred
RoHS Compliant

CY7C25632KV18-500BZXC

package

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CY7C25632KV18-500BZXC
CY7C25632KV18-500BZXC

Product details

  • Architecture
    QDR-II+, ODT
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 18
  • Density
    72 MBit
  • ECC
    N
  • Family
    QDR-II+, ODT
  • Frequency
    500 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4Mb x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    2.5
Recommended
OPN
CY7C25632KV18-500BZXC
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 680
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 680
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C25632KV18-500BZXC is a 72-Mbit QDR II+ synchronous pipelined SRAM in a 165-ball FBGA package, organized as 4M × 18 with separate read and write DDR ports for concurrent transactions. It supports up to 500 MHz clock (1.0 GHz data transfer), four-word burst, 2.5-cycle read latency (DOFF HIGH), on-die termination for D/BWS/K, and PLL-based timing. VDD 1.7–1.9 V; VDDQ 1.4 V to VDD.

Features

  • 550 MHz clock (1100 MHz DDR data)
  • Separate read and write data ports
  • Concurrent read/write transactions
  • Four-word burst architecture
  • 2.5-cycle read latency (DOFF HIGH)
  • 1-cycle read latency mode (DOFF LOW)
  • Two input clocks (K and K)
  • Echo clocks CQ/CQ for data capture
  • QVLD pin indicates valid read data
  • On-die termination for D/BWS/K
  • PLL runs down to 120 MHz
  • Core VDD 1.7 V to 1.9 V

Benefits

  • High bandwidth for fast DSP/ASIC
  • No bus turn-around delays
  • Read and write run in parallel
  • Lower address bus frequency
  • Deterministic 2.5-cycle reads
  • 1-cycle reads for low latency
  • Simpler DDR timing with K/K
  • Easier high-speed data capture
  • QVLD reduces timing margin effort
  • ODT cuts external termination BOM
  • PLL improves data placement margin
  • 1.8 V core reduces power vs 2.5 V

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