CY7C1612KV18-300BZXI
Active and preferred
RoHS Compliant

CY7C1612KV18-300BZXI

package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1612KV18-300BZXI
CY7C1612KV18-300BZXI

Product details

  • Architecture
    QDR-II
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 18
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II
  • Frequency
    300 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    8Mb x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1.5
Recommended
OPN
CY7C1612KV18-300BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1612KV18-300BZXI is a 144-Mbit QDR II synchronous pipelined SRAM in 8M × 18, with independent read and write ports for concurrent transactions. It supports a 300 MHz clock and DDR transfers for 600 MHz data rate, two-word burst accesses, echo clocks (CQ/CQ), and optional PLL/programmable impedance. Operates from 1.7–1.9 V VDD and 1.4 V–VDD VDDQ, in a 165-ball FBGA, industrial -40 to +85°C.

Features

  • Dual read/write data ports
  • 360 MHz clock operation
  • DDR I/O, 720 MHz data transfer
  • Two-word burst on all accesses
  • Two input clocks K and K
  • Separate output clocks C and C
  • Echo clocks CQ and CQ
  • 1.5-cycle read latency (DOFF=1)
  • 1-cycle read latency (DOFF=0)
  • 1.8 V VDD supply
  • VDDQ = 1.4 V to VDD
  • IEEE 1149.1-2001 JTAG TAP

Benefits

  • No bus turnaround, more bandwidth
  • Concurrent reads and writes
  • Fast throughput at 360 MHz
  • Echo clocks ease data capture
  • C/C clocks reduce skew issues
  • Flexible latency eases timing
  • PLL improves data placement
  • JTAG simplifies board test
  • Port selects enable depth scaling
  • VDDQ range eases I/O matching
  • Defined power-up prevents faults
  • Low SER improves data integrity

Applications

Documents

Design resources

Partner solutions

Developer community